Fix debug module reset state machine
dmactive should only go low when the debug module has successfully reset. Approximate this by waiting for 1024 cycles, allowing any register access requests and system bus requests to come back.
This commit is contained in:
Peter Rugg
@@ -150,6 +150,8 @@ module mkDebug_Module (Debug_Module_IFC);
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// Local verbosity: 0 = quiet; 1 = print DMI transactions
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Integer verbosity = 0;
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Reg #(Maybe#(DM_Reset_Count)) rg_reset_count <- mkReg(Valid(~0));
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// The three parts
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DM_Run_Control_IFC dm_run_control <- mkDM_Run_Control;
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DM_Abstract_Commands_IFC dm_abstract_commands <- mkDM_Abstract_Commands;
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@@ -158,13 +160,22 @@ module mkDebug_Module (Debug_Module_IFC);
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FIFO#(DM_Addr) f_read_addr <- mkFIFO1;
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// ================================================================
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// Reset all three parts when dm_run_control.dmactive is low
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// Reset all three parts: triggered when dm_run_control.dmactive is low
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rule rl_reset (! dm_run_control.dmactive);
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$display ("%0d: Debug_Module reset", cur_cycle);
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rule rl_reset_start (dm_run_control.dmactive_cleared && rg_reset_count == Invalid);
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rg_reset_count <= Valid(~0);
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endrule
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rule rl_reset_wait (rg_reset_count matches tagged Valid .c &&& c != 0);
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rg_reset_count <= Valid(c - 1);
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endrule
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rule rl_reset_done (rg_reset_count == Valid(0));
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$display ("%0d: Debug_Module reset complete", cur_cycle);
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dm_run_control.reset;
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dm_abstract_commands.reset;
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dm_system_bus.reset;
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rg_reset_count <= Invalid;
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endrule
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// ================================================================
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@@ -174,7 +185,7 @@ module mkDebug_Module (Debug_Module_IFC);
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// Facing GDB/DMI (Debug Module Interface)
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interface DMI dmi;
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method Action read_addr (DM_Addr dm_addr) if (dm_run_control.dmactive);
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method Action read_addr (DM_Addr dm_addr);
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f_read_addr.enq(dm_addr);
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if (verbosity != 0)
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@@ -241,58 +252,60 @@ module mkDebug_Module (Debug_Module_IFC);
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return dm_word;
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endmethod
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method Action write (DM_Addr dm_addr, DM_Word dm_word) if (dm_run_control.dmactive);
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method Action write (DM_Addr dm_addr, DM_Word dm_word);
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Bool handled = False;
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum0)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_verbosity)) begin
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if (rg_reset_count == Invalid) begin
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_dmstatus)
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|| (dm_addr == dm_addr_hartinfo)
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|| (dm_addr == dm_addr_haltsum0)
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|| (dm_addr == dm_addr_hawindowsel)
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|| (dm_addr == dm_addr_hawindow)
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|| (dm_addr == dm_addr_devtreeaddr0)
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|| (dm_addr == dm_addr_authdata)
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|| (dm_addr == dm_addr_verbosity)) begin
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dm_run_control.write (dm_addr, dm_word);
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handled = True;
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end
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dm_run_control.write (dm_addr, dm_word);
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handled = True;
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end
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0)) begin
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if ( (dm_addr == dm_addr_dmcontrol)
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|| (dm_addr == dm_addr_abstractcs)
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|| (dm_addr == dm_addr_command)
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|| (dm_addr == dm_addr_data0)
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|| (dm_addr == dm_addr_data1)
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|| (dm_addr == dm_addr_data2)
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|| (dm_addr == dm_addr_data3)
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|| (dm_addr == dm_addr_data4)
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|| (dm_addr == dm_addr_data5)
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|| (dm_addr == dm_addr_data6)
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|| (dm_addr == dm_addr_data7)
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|| (dm_addr == dm_addr_data8)
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|| (dm_addr == dm_addr_data9)
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|| (dm_addr == dm_addr_data10)
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|| (dm_addr == dm_addr_data11)
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|| (dm_addr == dm_addr_abstractauto)
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|| (dm_addr == dm_addr_progbuf0)) begin
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dm_abstract_commands.write (dm_addr, dm_word);
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handled = True;
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end
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dm_abstract_commands.write (dm_addr, dm_word);
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handled = True;
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end
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if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3)) begin
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if ( (dm_addr == dm_addr_sbcs)
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|| (dm_addr == dm_addr_sbaddress0)
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|| (dm_addr == dm_addr_sbaddress1)
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|| (dm_addr == dm_addr_sbaddress2)
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|| (dm_addr == dm_addr_sbdata0)
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|| (dm_addr == dm_addr_sbdata1)
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|| (dm_addr == dm_addr_sbdata2)
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|| (dm_addr == dm_addr_sbdata3)) begin
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dm_system_bus.write (dm_addr, dm_word);
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handled = True;
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end
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dm_system_bus.write (dm_addr, dm_word);
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handled = True;
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end
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end
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if (! handled) begin
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// TODO: set error status?
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