Fix debug module reset state machine

dmactive should only go low when the debug module has successfully
reset. Approximate this by waiting for 1024 cycles, allowing any
register access requests and system bus requests to come back.

src_Core/Debug_Module/DM_Common.bsv

@@ -26,6 +26,8 @@ DM_Addr max_DM_Addr = 'h5F;
 
 typedef Bit #(32) DM_Word;
 
+typedef Bit #(10) DM_Reset_Count;
+
 // ================================================================
 // Debug Module address map
 

src_Core/Debug_Module/DM_Run_Control.bsv

@@ -47,7 +47,7 @@ import ProcTypes :: *;
 // Interface
 
 interface DM_Run_Control_IFC;
-   method Bool   dmactive;
+   method Bool   dmactive_cleared;
    method Action reset;
 
    // ----------------
@@ -111,6 +111,8 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
    Reg #(Bool)     rg_dmcontrol_ndmreset  <- mkRegU;
    Reg #(Bool)     rg_dmcontrol_dmactive  <- mkReg (False);
    Reg #(Bit#(20)) rg_dmcontrol_hartsel   <- mkReg (0);
+   // Whether the user has attempted to clear dmactive since last reset
+   Reg #(Bool)     rg_dmactive_cleared    <- mkReg (False);
 
    Bit#(20) core_num_sel = fromInteger(valueOf(CoreNum));
 
@@ -193,7 +195,6 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	 rg_dmcontrol_haltreq   <= haltreq;
 	 rg_dmcontrol_hartreset <= hartreset;
 	 rg_dmcontrol_ndmreset  <= ndmreset;
-	 rg_dmcontrol_dmactive  <= dmactive;
 	 rg_dmcontrol_hartsel   <= hartsel;
 
 	 // Debug Module reset
@@ -214,12 +215,13 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	       $display ("    dmactive has priority; ignoring hartreset");
 	    end
 
-	    // No action here; other rules will fire (see method dmactive, Debug_Module.rl_reset)
-	    noAction;
-	 end
+	    rg_dmactive_cleared <= True;
+
+	 end else begin
+	    rg_dmcontrol_dmactive <= True;
 
 	    // Ignore if NDM reset is in progress
-	 else if (rg_ndm_reset_pending) begin
+	    if (rg_ndm_reset_pending) begin
 	       $display ("%0d: %m.dmcontrol_write 0x%0h: ndm reset in progress; ignoring this write",
 	                 cur_cycle, dm_word);
 	    end
@@ -298,6 +300,7 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
 	          $display ("%0d: %m.dmcontrol_write: hart %0d halt request", cur_cycle, hartsel);
 	       end
 	    end
+	 end
       endaction
    endfunction
 
@@ -355,8 +358,8 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
    // ----------------------------------------------------------------
    // INTERFACE
 
-   method Bool dmactive;
-      return rg_dmcontrol_dmactive;
+   method Bool dmactive_cleared;
+      return rg_dmactive_cleared;
    endmethod
 
    method Action reset;
@@ -375,7 +378,9 @@ module mkDM_Run_Control (DM_Run_Control_IFC);
       rg_dmcontrol_haltreq   <= False;
       rg_dmcontrol_hartreset <= False;
       rg_dmcontrol_ndmreset  <= False;
-      rg_dmcontrol_dmactive  <= True;    // DM module is now active
+      rg_dmcontrol_dmactive  <= False;  // Debug module stays inactive so debugger can confirm it has reset
+
+      rg_dmactive_cleared    <= False;
 
       writeVReg(rg_harts_hasreset, replicate(False));
       writeVReg(rg_harts_resumeack, replicate(False));

src_Core/Debug_Module/Debug_Module.bsv

@@ -150,6 +150,8 @@ module mkDebug_Module (Debug_Module_IFC);
    // Local verbosity: 0 = quiet; 1 = print DMI transactions
    Integer verbosity = 0;
 
+   Reg #(Maybe#(DM_Reset_Count)) rg_reset_count <- mkReg(Valid(~0));
+
    // The three parts
    DM_Run_Control_IFC        dm_run_control       <- mkDM_Run_Control;
    DM_Abstract_Commands_IFC  dm_abstract_commands <- mkDM_Abstract_Commands;
@@ -158,13 +160,22 @@ module mkDebug_Module (Debug_Module_IFC);
    FIFO#(DM_Addr) f_read_addr <- mkFIFO1;
 
    // ================================================================
-   // Reset all three parts when dm_run_control.dmactive is low
+   // Reset all three parts: triggered when dm_run_control.dmactive is low
 
-   rule rl_reset (! dm_run_control.dmactive);
-      $display ("%0d: Debug_Module reset", cur_cycle);
+   rule rl_reset_start (dm_run_control.dmactive_cleared && rg_reset_count == Invalid);
+      rg_reset_count <= Valid(~0);
+   endrule
+
+   rule rl_reset_wait (rg_reset_count matches tagged Valid .c &&& c != 0);
+      rg_reset_count <= Valid(c - 1);
+   endrule
+
+   rule rl_reset_done (rg_reset_count == Valid(0));
+      $display ("%0d: Debug_Module reset complete", cur_cycle);
       dm_run_control.reset;
       dm_abstract_commands.reset;
       dm_system_bus.reset;
+      rg_reset_count <= Invalid;
    endrule
 
    // ================================================================
@@ -174,7 +185,7 @@ module mkDebug_Module (Debug_Module_IFC);
    // Facing GDB/DMI (Debug Module Interface)
 
    interface DMI dmi;
-      method Action read_addr  (DM_Addr dm_addr) if (dm_run_control.dmactive);
+      method Action read_addr  (DM_Addr dm_addr);
 	 f_read_addr.enq(dm_addr);
 
 	 if (verbosity != 0)
@@ -241,10 +252,11 @@ module mkDebug_Module (Debug_Module_IFC);
 	 return dm_word;
       endmethod
 
-      method Action write (DM_Addr dm_addr, DM_Word dm_word) if (dm_run_control.dmactive);
+      method Action write (DM_Addr dm_addr, DM_Word dm_word);
 
 	 Bool handled = False;
 
+         if (rg_reset_count == Invalid) begin
 	    if (   (dm_addr == dm_addr_dmcontrol)
 	       || (dm_addr == dm_addr_dmstatus)
 	       || (dm_addr == dm_addr_hartinfo)
@@ -293,6 +305,7 @@ module mkDebug_Module (Debug_Module_IFC);
 	       dm_system_bus.write (dm_addr, dm_word);
 	       handled = True;
 	    end
+         end
 
 	 if (! handled) begin
 	    // TODO: set error status?