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Prevent various debug prints by default

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This commit is contained in:
Peter Rugg
2025-01-08 18:43:05 +00:00
parent d1bea2faf0
commit 1df304a820
6 changed files with 127 additions and 105 deletions
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1
src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
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@@ -1165,7 +1165,6 @@ module mkFetchStage(FetchStage);
if (iType == Br) begin
// Train the direction predictor for all branches
dirPred.update(taken, trainInfo.dir, mispred);
$display("Branch train PC: %x, taken: %x, mispred: %x", getAddr(pc), taken, mispred);
end
// train next addr pred when mispred
if(mispred) begin

2
src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
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@@ -271,7 +271,7 @@ interface MemExePipeline;
endinterface
module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
Bool verbose = True;
Bool verbose = False;
// we change cache request in case of single core, becaues our MSI protocol
// is not good with single core