From 1ef2d0cbebb3cc0393c81ffe385c6862fe39fb74 Mon Sep 17 00:00:00 2001
From: jon <>
Date: Tue, 9 Mar 2021 15:57:15 +0000
Subject: [PATCH] Include both execute redirect and commit redirect in
 "redirect" counter.

---
 src_Core/CPU/Core.bsv                             | 11 ++++-------
 src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 13 +++++++++++++
 2 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index 83bc436..39be25c 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -271,7 +271,7 @@ module mkCore#(CoreId coreId)(Core);
 `endif
 
 `ifdef PERFORMANCE_MONITORING
-   Array #(Reg #(EventsCore)) hpm_core_events <- mkDRegOR (5, unpack (0));
+   Array #(Reg #(EventsCore)) hpm_core_events <- mkDRegOR (2, unpack (0));
 `endif
 
    // ================================================================
@@ -416,11 +416,6 @@ module mkCore#(CoreId coreId)(Core);
 `endif
                     );
                     globalSpecUpdate.incorrectSpec(False, spec_tag, inst_tag);
-`ifdef PERFORMANCE_MONITORING
-                    EventsCore events = unpack (0);
-                    events.evt_REDIRECT = 1;
-                    hpm_core_events[1] <= events;
-`endif
                 endmethod
                 method correctSpec = globalSpecUpdate.correctSpec[finishAluCorrectSpecPort(i)].put;
                 method doStats = doStatsReg._read;
@@ -1103,7 +1098,9 @@ module mkCore#(CoreId coreId)(Core);
      Reg#(EventsCache) events_llc_reg <- mkRegU;
      Reg#(EventsCache) events_tgc_reg <- mkRegU;
      rule report_events;
-         hpm_core_events[2] <= unpack(pack(commitStage.events));
+         EventsCore events = unpack(pack(commitStage.events));
+         events.evt_REDIRECT = fetchStage.redirect_evt;
+         hpm_core_events[1] <= events;
      endrule
 
      Vector #(1, Bit #(Report_Width)) null_evt = replicate (0);
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 423e84d..895ffd9 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -75,6 +75,7 @@ import Types::*;
 `endif
 import IndexedMultiset::*;
 import Cur_Cycle :: *;
+import DReg :: *;
 
 // ================================================================
 // For fv_decode_C function and related types and definitions
@@ -154,6 +155,9 @@ interface FetchStage;
 
     // performance
     interface Perf#(DecStagePerfType) perf;
+`ifdef PERFORMANCE_MONITORING
+    method Bool redirect_evt;
+`endif
 endinterface
 
 // PC "compression" types to facilitate storing common upper PC bits in a
@@ -414,6 +418,9 @@ module mkFetchStage(FetchStage);
         });
     endrule
 `endif
+`ifdef PERFORMANCE_MONITORING
+    Reg#(Bool) redirect_evt <- mkDReg(False);
+`endif
 
     rule updatePcInBtb;
         nextAddrPred.put_pc(pc_reg[pc_final_port]);
@@ -897,6 +904,9 @@ module mkFetchStage(FetchStage);
         // this redirect may be caused by a trap/system inst in commit stage
         // we conservatively set wait for flush TODO make this an input parameter
         waitForFlush[2] <= True;
+`ifdef PERFORMANCE_MONITORING
+        redirect_evt <= True;
+`endif
     endmethod
 
 `ifdef INCLUDE_GDB_CONTROL
@@ -995,4 +1005,7 @@ module mkFetchStage(FetchStage);
 `endif
     endinterface
 
+`ifdef PERFORMANCE_MONITORING
+    method Bool redirect_evt = redirect_evt._read;
+`endif
 endmodule