From 1fbf78629428daa5cc90c1b21473ed3758214351 Mon Sep 17 00:00:00 2001 From: jon <> Date: Wed, 17 Feb 2021 21:26:54 +0000 Subject: [PATCH] Add to synthesis file set. --- src_SSITH_P3/xilinx_ip/component.xml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src_SSITH_P3/xilinx_ip/component.xml b/src_SSITH_P3/xilinx_ip/component.xml index 23588ae..a5269ec 100644 --- a/src_SSITH_P3/xilinx_ip/component.xml +++ b/src_SSITH_P3/xilinx_ip/component.xml @@ -2521,6 +2521,11 @@ verilogSource IMPORTED_FILE + + hdl/mkPerfCountersToooba.v + verilogSource + IMPORTED_FILE + hdl/mkRFileSynth.v verilogSource