A design that actually passes one performance monitor trace from

TestRig.  The example counted redirections, which happend to match
between Flute and Toooba for this example.

src_Core/RISCY_OOO/procs/lib/CSRs.bsvi

@@ -37,6 +37,101 @@
 `CSR(MIP,        12'h344)
 `CSR(MCYCLE,     12'hb00)
 `CSR(MINSTRET,   12'hb02)
+
+`ifdef PERFORMANCE_MONITORING
+`CSR(HPMCNT3,   12'hc03)
+`CSR(HPMCNT4,   12'hc04)
+`CSR(HPMCNT5,   12'hc05)
+`CSR(HPMCNT6,   12'hc06)
+`CSR(HPMCNT7,   12'hc07)
+`CSR(HPMCNT8,   12'hc08)
+`CSR(HPMCNT9,   12'hc09)
+`CSR(HPMCNT10,   12'hc0a)
+`CSR(HPMCNT11,   12'hc0b)
+`CSR(HPMCNT12,   12'hc0c)
+`CSR(HPMCNT13,   12'hc0d)
+`CSR(HPMCNT14,   12'hc0e)
+`CSR(HPMCNT15,   12'hc0f)
+`CSR(HPMCNT16,   12'hc10)
+`CSR(HPMCNT17,   12'hc11)
+`CSR(HPMCNT18,   12'hc12)
+`CSR(HPMCNT19,   12'hc13)
+`CSR(HPMCNT20,   12'hc14)
+`CSR(HPMCNT21,   12'hc15)
+`CSR(HPMCNT22,   12'hc16)
+`CSR(HPMCNT23,   12'hc17)
+`CSR(HPMCNT24,   12'hc18)
+`CSR(HPMCNT25,   12'hc19)
+`CSR(HPMCNT26,   12'hc1a)
+`CSR(HPMCNT27,   12'hc1b)
+`CSR(HPMCNT28,   12'hc1c)
+`CSR(HPMCNT29,   12'hc1d)
+`CSR(HPMCNT30,   12'hc1e)
+`CSR(HPMCNT31,   12'hc1f)
+
+`CSR(MHPMCNT3,    12'hb03)
+`CSR(MHPMCNT4,    12'hb04)
+`CSR(MHPMCNT5,    12'hb05)
+`CSR(MHPMCNT6,    12'hb06)
+`CSR(MHPMCNT7,    12'hb07)
+`CSR(MHPMCNT8,    12'hb08)
+`CSR(MHPMCNT9,    12'hb09)
+`CSR(MHPMCNT10,   12'hb0a)
+`CSR(MHPMCNT11,   12'hb0b)
+`CSR(MHPMCNT12,   12'hb0c)
+`CSR(MHPMCNT13,   12'hb0d)
+`CSR(MHPMCNT14,   12'hb0e)
+`CSR(MHPMCNT15,   12'hb0f)
+`CSR(MHPMCNT16,   12'hb10)
+`CSR(MHPMCNT17,   12'hb11)
+`CSR(MHPMCNT18,   12'hb12)
+`CSR(MHPMCNT19,   12'hb13)
+`CSR(MHPMCNT20,   12'hb14)
+`CSR(MHPMCNT21,   12'hb15)
+`CSR(MHPMCNT22,   12'hb16)
+`CSR(MHPMCNT23,   12'hb17)
+`CSR(MHPMCNT24,   12'hb18)
+`CSR(MHPMCNT25,   12'hb19)
+`CSR(MHPMCNT26,   12'hb1a)
+`CSR(MHPMCNT27,   12'hb1b)
+`CSR(MHPMCNT28,   12'hb1c)
+`CSR(MHPMCNT29,   12'hb1d)
+`CSR(MHPMCNT30,   12'hb1e)
+`CSR(MHPMCNT31,   12'hb1f)
+
+`CSR(MCNTIHB,     12'h320) // Machine Counter-Inhibit
+
+`CSR(MHPMEVENT3,    12'h323)
+`CSR(MHPMEVENT4,    12'h324)
+`CSR(MHPMEVENT5,    12'h325)
+`CSR(MHPMEVENT6,    12'h326)
+`CSR(MHPMEVENT7,    12'h327)
+`CSR(MHPMEVENT8,    12'h328)
+`CSR(MHPMEVENT9,    12'h329)
+`CSR(MHPMEVENT10,   12'h32a)
+`CSR(MHPMEVENT11,   12'h32b)
+`CSR(MHPMEVENT12,   12'h32c)
+`CSR(MHPMEVENT13,   12'h32d)
+`CSR(MHPMEVENT14,   12'h32e)
+`CSR(MHPMEVENT15,   12'h32f)
+`CSR(MHPMEVENT16,   12'h330)
+`CSR(MHPMEVENT17,   12'h331)
+`CSR(MHPMEVENT18,   12'h332)
+`CSR(MHPMEVENT19,   12'h333)
+`CSR(MHPMEVENT20,   12'h334)
+`CSR(MHPMEVENT21,   12'h335)
+`CSR(MHPMEVENT22,   12'h336)
+`CSR(MHPMEVENT23,   12'h337)
+`CSR(MHPMEVENT24,   12'h338)
+`CSR(MHPMEVENT25,   12'h339)
+`CSR(MHPMEVENT26,   12'h33a)
+`CSR(MHPMEVENT27,   12'h33b)
+`CSR(MHPMEVENT28,   12'h33c)
+`CSR(MHPMEVENT29,   12'h33d)
+`CSR(MHPMEVENT30,   12'h33e)
+`CSR(MHPMEVENT31,   12'h33f)
+`endif // PERFORMANCE_MONITORING
+
 `CSR(MVENDORID,  12'hf11)
 `CSR(MARCHID,    12'hf12)
 `CSR(MIMPID,     12'hf13)

src_Core/RISCY_OOO/procs/lib/ProcTypes.bsv

@@ -1040,3 +1040,9 @@ function Fmt showInst(Instruction inst);
 endfunction
 
 function x addPc(x cap, Bit#(12) inc) provisos (Add#(f, 12, c), CHERICap::CHERICap#(x, a, b, c, d, e)) = setAddrUnsafe(cap, getAddr(cap) + signExtend(inc));
+
+`ifdef PERFORMANCE_MONITORING
+typedef 96 No_Of_Evts;
+typedef 64 Counter_Width;
+typedef 29 No_Of_Ctrs;
+`endif