From 28abd5de95ed0a96105a308bcca31b83485838c8 Mon Sep 17 00:00:00 2001 From: Akilan Date: Tue, 23 Dec 2025 09:34:06 +0000 Subject: [PATCH] test traces and log file for TLB check --- .../test.txt | 33601 ++++++++++++++++ src_Core/CPU/MMIOPlatform.bsv | 10 +- src_Core/Core/Trace_Data2_to_Trace_Data.bsv | 8 +- 3 files changed, 33610 insertions(+), 9 deletions(-) create mode 100644 builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt new file mode 100644 index 0000000..d9982cb --- /dev/null +++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt @@ -0,0 +1,33601 @@ +make -C ../../Tests/elf_to_hex +make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex' +make[1]: 'elf_to_hex' is up to date. +make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/Toooba/Tests/elf_to_hex' +../../Tests/elf_to_hex/elf_to_hex ../../Tests/isa/rv64um-v-mulw Mem.hex +c_mem_load_elf: ../../Tests/isa/rv64um-v-mulw is a 64-bit ELF file +Section .text.init : addr 80000000 to addr 80000174; size 0x 174 (= 372) bytes +Section .tohost : addr 80001000 to addr 80001048; size 0x 48 (= 72) bytes +Section .text : addr 80002000 to addr 80002ed0; size 0x ed0 (= 3792) bytes +Section .rodata.str1.8 : addr 80002ed0 to addr 800030b0; size 0x 1e0 (= 480) bytes +Section .bss : addr 80004000 to addr 800087f0; size 0x 47f0 (= 18416) bytes +Section .riscv.attributes: Ignored +Section .comment : Ignored +Section .symtab : Searching for addresses of '_start', 'exit' and 'tohost' symbols +Writing symbols to: symbol_table.txt + No 'exit' label found +Section .strtab : Ignored +Section .shstrtab : Ignored +Min addr: 80000000 (hex) +Max addr: 800087ef (hex) +Writing mem hex to file 'Mem.hex' +Subtracting 0x80000000 base from addresses +./exe_HW_sim +v1 +tohost +Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 1088 to 33554430. +1: top.soc_top.rl_reset_start_initial ... +11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000 + SoC address map: + Boot ROM: 0x1000 .. 0x2000 + Mem0 Controller: 0x80000000 .. 0xc0000000 + UART0: 0xc0000000 .. 0xc0000080 +11: top.soc_top.rl_reset_complete_initial +================================================================ +Bluespec RISC-V standalone system simulation v1.2 +Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved. +================================================================ +INFO: watch_tohost 1, tohost_addr = 0x80001000, fromhost_addr = 0x0 +12: top.soc_top.method start (tohost 80001000, fromhost 0) +100: top.soc_top.rl_step_0, n = 0, do_release +100: top.soc_top do_release(restartRunning: True, to_host_addr: 0) +100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0 +101: top.soc_top.rl_ctrl_req +101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 80001000, fromhostAddr 0 +101: top.soc_top do_release(restartRunning: True, to_host_addr: 80001000) +instret:0 PC:0x1ffff0000000000000000000000001000 instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 167 +instret:1 PC:0x1ffff0000000000000000000000001004 instr:0x02028593 iType:Alu [doCommitNormalInst [0]] 168 +instret:2 PC:0x1ffff0000000000000000000000001008 instr:0xf1402573 iType:Csr [doCommitSystemInst] 224 +instret:3 PC:0x1ffff000000000000000000000000100c instr:0x0182b283 iType:Ld [doCommitNormalInst [0]] 403 +instret:4 PC:0x1ffff0000000000000000000000001010 instr:0x00028067 iType:Jr [doCommitNormalInst [0]] 408 +instret:5 PC:0x1ffff0000000000000000000080000000 instr:0x00c0006f iType:J [doCommitNormalInst [0]] 1155 +instret:6 PC:0x1ffff000000000000000000008000000c instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 1158 +instret:7 PC:0x1ffff0000000000000000000080000010 instr:0xffc28293 iType:Alu [doCommitNormalInst [0]] 1159 +instret:8 PC:0x1ffff0000000000000000000080000014 instr:0x30529073 iType:Scr [doCommitSystemInst] 1165 +instret:9 PC:0x1ffff0000000000000000000080000018 instr:0x00009117 iType:Auipc [doCommitNormalInst [0]] 1218 +instret:10 PC:0x1ffff000000000000000000008000001c instr:0x6b810113 iType:Alu [doCommitNormalInst [0]] 1219 +instret:11 PC:0x1ffff0000000000000000000080000020 instr:0xf14022f3 iType:Csr [doCommitSystemInst] 1225 +instret:12 PC:0x1ffff0000000000000000000080000024 instr:0x00c29293 iType:Alu [doCommitNormalInst [0]] 1277 +instret:13 PC:0x1ffff0000000000000000000080000028 instr:0x00510133 iType:Alu [doCommitNormalInst [0]] 1278 +instret:14 PC:0x1ffff000000000000000000008000002c instr:0x34011073 iType:Csr [doCommitSystemInst] 1284 +instret:15 PC:0x1ffff0000000000000000000080000030 instr:0x2a9020ef iType:J [doCommitNormalInst [0]] 1339 +instret:16 PC:0x1ffff0000000000000000000080002ad8 instr:0x00008067 iType:Jr [doCommitNormalInst [0]] 1340 +instret:17 PC:0x1ffff0000000000000000000080000034 instr:0x00003517 iType:Auipc [doCommitNormalInst [0]] 1341 +instret:18 PC:0x1ffff0000000000000000000080000038 instr:0xaa850513 iType:Alu [doCommitNormalInst [0]] 1342 +instret:19 PC:0x1ffff000000000000000000008000003c instr:0x0a50206f iType:J [doCommitNormalInst [1]] 1342 +instret:20 PC:0x1ffff00000000000000000000800028e0 instr:0xf14027f3 iType:Csr [doCommitSystemInst] 1348 +instret:21 PC:0x1ffff00000000000000000000800028e4 instr:0x18079c63 iType:Br [doCommitNormalInst [0]] 1400 +instret:22 PC:0x1ffff00000000000000000000800028e8 instr:0x00002697 iType:Auipc [doCommitNormalInst [1]] 1400 +instret:23 PC:0x1ffff00000000000000000000800028ec instr:0x71868693 iType:Alu [doCommitNormalInst [0]] 1401 +instret:24 PC:0x1ffff00000000000000000000800028f0 instr:0x00003717 iType:Auipc [doCommitNormalInst [1]] 1401 +instret:25 PC:0x1ffff00000000000000000000800028f4 instr:0x71070713 iType:Alu [doCommitNormalInst [0]] 1402 +instret:26 PC:0x1ffff00000000000000000000800028f8 instr:0x00c6d693 iType:Alu [doCommitNormalInst [1]] 1402 +instret:27 PC:0x1ffff00000000000000000000800028fc instr:0x00c75713 iType:Alu [doCommitNormalInst [0]] 1403 +instret:28 PC:0x1ffff0000000000000000000080002900 instr:0x00004797 iType:Auipc [doCommitNormalInst [0]] 1404 +instret:29 PC:0x1ffff0000000000000000000080002904 instr:0x70078793 iType:Alu [doCommitNormalInst [0]] 1405 +instret:30 PC:0x1ffff0000000000000000000080002908 instr:0x00a69693 iType:Alu [doCommitNormalInst [0]] 1406 +instret:31 PC:0x1ffff000000000000000000008000290c instr:0x00a71713 iType:Alu [doCommitNormalInst [1]] 1406 +instret:32 PC:0x1ffff0000000000000000000080002910 instr:0x0016e693 iType:Alu [doCommitNormalInst [0]] 1407 +instret:33 PC:0x1ffff0000000000000000000080002914 instr:0x00176713 iType:Alu [doCommitNormalInst [1]] 1407 +instret:34 PC:0x1ffff0000000000000000000080002918 instr:0x00c7d793 iType:Alu [doCommitNormalInst [0]] 1408 +instret:35 PC:0x1ffff000000000000000000008000291c instr:0x00001897 iType:Auipc [doCommitNormalInst [1]] 1408 +instret:36 PC:0x1ffff0000000000000000000080002920 instr:0x6ed8b223 iType:St [doCommitNormalInst [0]] 1409 +instret:37 PC:0x1ffff0000000000000000000080002924 instr:0x00a79793 iType:Alu [doCommitNormalInst [1]] 1409 + 14100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha920 } +instret:38 PC:0x1ffff0000000000000000000080002928 instr:0x00002697 iType:Auipc [doCommitNormalInst [0]] 1410 + 14110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha920 } + 14110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:39 PC:0x1ffff000000000000000000008000292c instr:0x6ce6b823 iType:St [doCommitNormalInst [0]] 1411 +instret:40 PC:0x1ffff0000000000000000000080002930 instr:0x20000737 iType:Alu [doCommitNormalInst [1]] 1411 +instret:41 PC:0x1ffff0000000000000000000080002934 instr:0x0cf70713 iType:Alu [doCommitNormalInst [0]] 1412 +instret:42 PC:0x1ffff0000000000000000000080002938 instr:0xfff00593 iType:Alu [doCommitNormalInst [1]] 1412 + 14130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha920 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080004000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:43 PC:0x1ffff000000000000000000008000293c instr:0x0017e793 iType:Alu [doCommitNormalInst [0]] 1413 +instret:44 PC:0x1ffff0000000000000000000080002940 instr:0x00001617 iType:Auipc [doCommitNormalInst [0]] 1463 +instret:45 PC:0x1ffff0000000000000000000080002944 instr:0x6c060613 iType:Alu [doCommitNormalInst [0]] 1464 +instret:46 PC:0x1ffff0000000000000000000080002948 instr:0xed010113 iType:Alu [doCommitNormalInst [1]] 1464 +instret:47 PC:0x1ffff000000000000000000008000294c instr:0x03f59813 iType:Alu [doCommitNormalInst [0]] 1465 +instret:48 PC:0x1ffff0000000000000000000080002950 instr:0x00004697 iType:Auipc [doCommitNormalInst [1]] 1465 +instret:49 PC:0x1ffff0000000000000000000080002954 instr:0x6ae6b423 iType:St [doCommitNormalInst [0]] 1466 +instret:50 PC:0x1ffff0000000000000000000080002958 instr:0x00002717 iType:Auipc [doCommitNormalInst [1]] 1466 +instret:51 PC:0x1ffff000000000000000000008000295c instr:0x6af73423 iType:St [doCommitNormalInst [0]] 1467 +instret:52 PC:0x1ffff0000000000000000000080002960 instr:0x00c65793 iType:Alu [doCommitNormalInst [1]] 1467 +instret:53 PC:0x1ffff0000000000000000000080002964 instr:0x12113423 iType:St [doCommitNormalInst [0]] 1468 +instret:54 PC:0x1ffff0000000000000000000080002968 instr:0x12813023 iType:St [doCommitNormalInst [0]] 1469 +instret:55 PC:0x1ffff000000000000000000008000296c instr:0x0107e7b3 iType:Alu [doCommitNormalInst [1]] 1469 + 14860 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080004000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 14870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 14870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080004000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha920 } + 14870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 14880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha92c } + 14890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 14890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha92c } + 14890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 14910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha92c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080004ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 15810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080004ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080004ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha92c } + 15820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 15830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080006ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha954 } + 15840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 15840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080006ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha954 } + 15840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 15860 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080006ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha954 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080006ff8, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 16790 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080006ff8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 16800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16800 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 16800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080006ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha954 } + 16800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 16810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha95c } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha95c } + 16820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 16840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha95c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080005000, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 17320 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080005000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040002, cs: M, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080005000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha95c } + 17330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha964 } + 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha964 } + 17350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 17370 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha964 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800096c8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 17850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800096c8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 17860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 17860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha964 } + 17860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 17870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha968 } + 17880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 17880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha968 } + 17880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 17880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha968 } + 17880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:56 PC:0x1ffff0000000000000000000080002970 instr:0x18079073 iType:Csr [doCommitSystemInst] 1789 +instret:57 PC:0x1ffff0000000000000000000080002974 instr:0x01f00793 iType:Alu [doCommitNormalInst [0]] 2064 +instret:58 PC:0x1ffff0000000000000000000080002978 instr:0x00b5d593 iType:Alu [doCommitNormalInst [1]] 2064 +instret:59 PC:0x1ffff000000000000000000008000297c instr:0x00000297 iType:Auipc [doCommitNormalInst [0]] 2065 +instret:60 PC:0x1ffff0000000000000000000080002980 instr:0x01428293 iType:Alu [doCommitNormalInst [0]] 2066 +instret:61 PC:0x1ffff0000000000000000000080002984 instr:0x305292f3 iType:Scr [doCommitSystemInst] 2072 +instret:62 PC:0x1ffff0000000000000000000080002988 instr:0x3b059073 iType:Csr [doCommitTrap] 2080 +instret:63 PC:0x1ffff0000000000000000000080002990 instr:0xbff00813 iType:Alu [doCommitNormalInst [0]] 2093 +instret:64 PC:0x1ffff0000000000000000000080002994 instr:0x01581813 iType:Alu [doCommitNormalInst [0]] 2094 +instret:65 PC:0x1ffff0000000000000000000080002998 instr:0xffffd797 iType:Auipc [doCommitNormalInst [1]] 2094 +instret:66 PC:0x1ffff000000000000000000008000299c instr:0x73078793 iType:Alu [doCommitNormalInst [0]] 2095 +instret:67 PC:0x1ffff00000000000000000000800029a0 instr:0x010787b3 iType:Alu [doCommitNormalInst [0]] 2096 +instret:68 PC:0x1ffff00000000000000000000800029a4 instr:0x10579073 iType:Scr [doCommitSystemInst] 2102 +instret:69 PC:0x1ffff00000000000000000000800029a8 instr:0x340027f3 iType:Csr [doCommitSystemInst] 2152 +instret:70 PC:0x1ffff00000000000000000000800029ac instr:0x010787b3 iType:Alu [doCommitNormalInst [0]] 2164 +instret:71 PC:0x1ffff00000000000000000000800029b0 instr:0x14079073 iType:Csr [doCommitSystemInst] 2170 +instret:72 PC:0x1ffff00000000000000000000800029b4 instr:0x0000b7b7 iType:Alu [doCommitNormalInst [0]] 2182 +instret:73 PC:0x1ffff00000000000000000000800029b8 instr:0x1007879b iType:Alu [doCommitNormalInst [0]] 2183 +instret:74 PC:0x1ffff00000000000000000000800029bc instr:0x30279073 iType:Csr [doCommitSystemInst] 2189 +instret:75 PC:0x1ffff00000000000000000000800029c0 instr:0x0001e7b7 iType:Alu [doCommitNormalInst [0]] 2201 +instret:76 PC:0x1ffff00000000000000000000800029c4 instr:0x30079073 iType:Csr [doCommitSystemInst] 2207 +instret:77 PC:0x1ffff00000000000000000000800029c8 instr:0x30405073 iType:Csr [doCommitSystemInst] 2219 +instret:78 PC:0x1ffff00000000000000000000800029cc instr:0x00005697 iType:Auipc [doCommitNormalInst [0]] 2231 +instret:79 PC:0x1ffff00000000000000000000800029d0 instr:0x63468693 iType:Alu [doCommitNormalInst [0]] 2232 +instret:80 PC:0x1ffff00000000000000000000800029d4 instr:0x010687b3 iType:Alu [doCommitNormalInst [0]] 2233 +instret:81 PC:0x1ffff00000000000000000000800029d8 instr:0x3e078713 iType:Alu [doCommitNormalInst [0]] 2234 +instret:82 PC:0x1ffff00000000000000000000800029dc instr:0x00006617 iType:Auipc [doCommitNormalInst [1]] 2234 +instret:83 PC:0x1ffff00000000000000000000800029e0 instr:0xe0f63623 iType:St [doCommitNormalInst [0]] 2235 +instret:84 PC:0x1ffff00000000000000000000800029e4 instr:0x00006797 iType:Auipc [doCommitNormalInst [1]] 2235 + 22360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e0 } +instret:85 PC:0x1ffff00000000000000000000800029e8 instr:0xdee7be23 iType:St [doCommitNormalInst [0]] 2236 +instret:86 PC:0x1ffff00000000000000000000800029ec instr:0x00006317 iType:Auipc [doCommitNormalInst [1]] 2236 + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e0 } + 22370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:87 PC:0x1ffff00000000000000000000800029f0 instr:0xa0430313 iType:Alu [doCommitNormalInst [0]] 2237 +instret:88 PC:0x1ffff00000000000000000000800029f4 instr:0x01100793 iType:Alu [doCommitNormalInst [1]] 2237 +instret:89 PC:0x1ffff00000000000000000000800029f8 instr:0x000808b7 iType:Alu [doCommitNormalInst [0]] 2238 +instret:90 PC:0x1ffff00000000000000000000800029fc instr:0x01080813 iType:Alu [doCommitNormalInst [1]] 2238 + 22390 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e0 } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800087e8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:91 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2289 +instret:92 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2290 +instret:93 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2290 +instret:94 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2291 +instret:95 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2291 +instret:96 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2292 +instret:97 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2292 +instret:98 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2293 +instret:99 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2293 +instret:100 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2294 +instret:101 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2295 +instret:102 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2295 +instret:103 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2297 +instret:104 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2297 +instret:105 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2298 + 23120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800087e8, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e0 } + 23130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e8 } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e8 } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha9e8 } + 23150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008000, fromState: I, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +instret:106 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2353 +instret:107 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2354 +instret:108 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2354 +instret:109 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2355 +instret:110 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2355 +instret:111 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2356 +instret:112 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2356 +instret:113 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2357 +instret:114 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2357 +instret:115 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2358 +instret:116 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2359 +instret:117 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2359 +instret:118 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2361 +instret:119 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2361 +instret:120 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2362 +instret:121 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2369 +instret:122 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2370 +instret:123 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2370 +instret:124 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2371 +instret:125 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2371 +instret:126 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2372 +instret:127 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2372 +instret:128 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2373 +instret:129 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2373 + 23740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +instret:130 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2374 + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:131 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2375 +instret:132 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2375 + 23760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:133 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2377 +instret:134 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2377 + 23780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:135 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2378 + 23790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 23850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:136 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2385 + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 23860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800080a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:137 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2386 +instret:138 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2386 + 23870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800080a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:139 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2387 +instret:140 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2387 + 23880 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008060, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:141 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2388 +instret:142 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2388 + 23890 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800080a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800080a0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 23890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800080a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:143 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2389 +instret:144 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2389 + 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800080a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 23900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:145 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2390 + 23910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:146 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2391 +instret:147 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2391 + 23930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 23930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:148 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2393 +instret:149 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2393 + 23940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:150 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2394 + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 23950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:151 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2401 +instret:152 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2402 +instret:153 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2402 +instret:154 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2403 +instret:155 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2403 +instret:156 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2404 +instret:157 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2404 +instret:158 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2405 +instret:159 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2405 +instret:160 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2406 + 24070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:161 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2407 +instret:162 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2407 + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:163 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2409 +instret:164 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2409 +instret:165 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2410 +instret:166 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2417 +instret:167 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2418 +instret:168 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2418 +instret:169 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2419 +instret:170 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2419 +instret:171 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2420 +instret:172 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2420 +instret:173 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2421 +instret:174 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2421 +instret:175 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2422 +instret:176 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2423 +instret:177 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2423 +instret:178 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2425 +instret:179 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2425 +instret:180 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2426 +instret:181 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2433 +instret:182 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2434 +instret:183 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2434 +instret:184 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2435 +instret:185 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2435 + 24360 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008060, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:186 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2436 +instret:187 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2436 + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +instret:188 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2437 +instret:189 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2437 + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:190 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2438 + 24390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:191 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2439 +instret:192 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2439 + 24400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800080c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:193 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2441 +instret:194 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2441 + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800080c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 24420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:195 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2442 + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800080c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 24440 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800080c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800080c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800080c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 24440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:196 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2449 +instret:197 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2450 +instret:198 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2450 +instret:199 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2451 +instret:200 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2451 +instret:201 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2452 +instret:202 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2452 +instret:203 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2453 +instret:204 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2453 +instret:205 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2454 + 24550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:206 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2455 +instret:207 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2455 + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:208 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2457 +instret:209 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2457 + 24580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:210 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2458 + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:211 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2465 +instret:212 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2466 +instret:213 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2466 + 24670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800080a0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:214 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2467 +instret:215 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2467 + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800080a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:216 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2468 +instret:217 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2468 +instret:218 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2469 +instret:219 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2469 +instret:220 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2470 + 24710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:221 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2471 +instret:222 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2471 + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:223 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2473 +instret:224 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2473 + 24740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:225 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2474 + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 24750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 24770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 24780 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008100, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:226 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2481 +instret:227 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2482 +instret:228 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2482 +instret:229 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2483 +instret:230 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2483 +instret:231 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2484 +instret:232 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2484 +instret:233 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2485 +instret:234 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2485 +instret:235 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2486 + 24870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:236 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2487 +instret:237 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2487 + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 24890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:238 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2489 +instret:239 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2489 + 24900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:240 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2490 + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 24910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:241 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2497 + 24980 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800080c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:242 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2498 +instret:243 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2498 + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800080c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 24990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:244 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2499 +instret:245 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2499 +instret:246 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2500 +instret:247 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2500 +instret:248 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2501 +instret:249 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2501 +instret:250 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2502 + 25030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800080a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:251 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2503 +instret:252 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2503 + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800080a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800080a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:253 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2505 +instret:254 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2505 + 25060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:255 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2506 + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:256 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2513 +instret:257 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2514 +instret:258 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2514 +instret:259 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2515 +instret:260 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2515 +instret:261 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2516 +instret:262 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2516 +instret:263 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2517 +instret:264 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2517 +instret:265 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2518 + 25190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:266 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2519 +instret:267 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2519 + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:268 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2521 +instret:269 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2521 + 25220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:270 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2522 + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008100, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:271 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [0]] 2529 + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:272 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2530 +instret:273 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2530 +instret:274 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2531 +instret:275 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2531 +instret:276 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2532 +instret:277 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2532 +instret:278 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2533 +instret:279 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2533 +instret:280 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2534 + 25350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:281 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2535 +instret:282 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2535 + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:283 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2536 +instret:284 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2536 + 25370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:285 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2537 +instret:286 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2537 + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:287 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2538 +instret:288 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2538 + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:289 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2539 +instret:290 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2539 + 25400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:291 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2540 +instret:292 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2540 + 25410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008140, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:293 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2541 +instret:294 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2541 +instret:295 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2542 + 25430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:296 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2543 +instret:297 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2543 + 25440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800080d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:298 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2544 +instret:299 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2544 + 25450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:300 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2545 +instret:301 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2545 + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800080d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:302 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2546 +instret:303 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2546 +instret:304 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2547 +instret:305 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2547 +instret:306 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2548 +instret:307 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2548 +instret:308 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2549 +instret:309 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2549 +instret:310 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2550 + 25510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:311 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2551 +instret:312 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2551 + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800080e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:313 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2552 +instret:314 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2552 + 25530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800080e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:315 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2553 +instret:316 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2553 + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800080e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800080e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:317 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2554 +instret:318 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2554 +instret:319 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2555 +instret:320 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2555 +instret:321 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2556 +instret:322 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2556 +instret:323 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2557 +instret:324 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2557 +instret:325 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2558 + 25590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:326 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2559 +instret:327 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2559 + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800080f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:328 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2560 +instret:329 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2560 + 25610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:330 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2561 +instret:331 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2561 + 25620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800080f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:332 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2562 +instret:333 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2562 +instret:334 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2563 +instret:335 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2563 +instret:336 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2564 +instret:337 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2564 +instret:338 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2565 +instret:339 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2565 +instret:340 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2566 + 25670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:341 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2567 +instret:342 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2567 + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:343 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2568 +instret:344 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2568 + 25690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:345 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2569 +instret:346 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2569 + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 25700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:347 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2570 +instret:348 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2570 + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:349 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2571 +instret:350 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2571 + 25720 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:351 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2572 +instret:352 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2572 + 25730 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008180, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +instret:353 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2573 +instret:354 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2573 +instret:355 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2574 + 25750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:356 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2575 +instret:357 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2575 + 25760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:358 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2576 +instret:359 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2576 + 25770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:360 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2577 +instret:361 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2577 + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:362 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2578 +instret:363 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2578 +instret:364 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2579 +instret:365 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2579 +instret:366 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2580 +instret:367 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2580 +instret:368 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2581 +instret:369 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2581 +instret:370 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2582 + 25830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:371 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2583 +instret:372 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2583 + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:373 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2584 +instret:374 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2584 + 25850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:375 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2585 +instret:376 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2585 + 25860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:377 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2586 +instret:378 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2586 +instret:379 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2587 +instret:380 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2587 +instret:381 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2588 +instret:382 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2588 + 25890 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008140, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:383 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2589 +instret:384 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2589 + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 25900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:385 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2590 + 25910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:386 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2591 +instret:387 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2591 + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 25920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:388 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2592 +instret:389 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2592 + 25930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:390 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2593 +instret:391 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2593 + 25940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 25940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 25940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 25940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:392 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2594 +instret:393 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2594 +instret:394 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2595 +instret:395 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2595 +instret:396 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2596 +instret:397 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2596 +instret:398 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2597 +instret:399 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2597 +instret:400 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2598 + 25990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:401 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2599 +instret:402 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2599 + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:403 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2600 +instret:404 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2600 + 26010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:405 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2601 +instret:406 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2601 + 26020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800081c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:407 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2602 +instret:408 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2602 + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800081c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:409 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2603 +instret:410 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2603 + 26040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800081c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:411 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2604 +instret:412 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2604 + 26050 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800081c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800081c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800081c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +instret:413 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2605 +instret:414 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2605 +instret:415 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2606 + 26070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:416 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2607 +instret:417 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2607 + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:418 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2608 +instret:419 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2608 + 26090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:420 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2609 +instret:421 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2609 + 26100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:422 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2610 +instret:423 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2610 +instret:424 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2611 +instret:425 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2611 +instret:426 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2612 +instret:427 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2612 +instret:428 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2613 +instret:429 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2613 +instret:430 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2614 + 26150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:431 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2615 +instret:432 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2615 + 26160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:433 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2616 +instret:434 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2616 + 26170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:435 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2617 +instret:436 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2617 + 26180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:437 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2618 +instret:438 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2618 +instret:439 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2619 +instret:440 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2619 +instret:441 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2620 +instret:442 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2620 + 26210 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008180, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:443 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2621 +instret:444 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2621 + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:445 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2622 + 26230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:446 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2623 +instret:447 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2623 + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:448 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2624 +instret:449 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2624 + 26250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:450 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2625 +instret:451 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2625 + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:452 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2626 +instret:453 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2626 +instret:454 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2627 +instret:455 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2627 +instret:456 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2628 +instret:457 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2628 +instret:458 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2629 +instret:459 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2629 +instret:460 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2630 + 26310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:461 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2631 +instret:462 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2631 + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:463 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2632 +instret:464 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2632 + 26330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:465 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2633 +instret:466 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2633 + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:467 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2634 +instret:468 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2634 + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:469 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2635 +instret:470 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2635 + 26360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:471 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2636 +instret:472 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2636 + 26370 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008200, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:473 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2637 +instret:474 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2637 +instret:475 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2638 + 26390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:476 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2639 +instret:477 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2639 + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:478 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2640 +instret:479 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2640 + 26410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:480 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2641 +instret:481 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2641 + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:482 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2642 +instret:483 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2642 +instret:484 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2643 +instret:485 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2643 +instret:486 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2644 +instret:487 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2644 +instret:488 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2645 +instret:489 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2645 +instret:490 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2646 + 26470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800081a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:491 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2647 +instret:492 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2647 + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800081a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800081a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:493 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2648 +instret:494 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2648 + 26490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:495 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2649 +instret:496 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2649 + 26500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:497 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2650 +instret:498 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2650 +instret:499 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2651 +instret:500 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2651 +instret:501 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2652 +instret:502 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2652 + 26530 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800081c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:503 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2653 +instret:504 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2653 + 26540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800081c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:505 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2654 + 26550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:506 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2655 +instret:507 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2655 + 26560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:508 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2656 +instret:509 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2656 + 26570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:510 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2657 +instret:511 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2657 + 26580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:512 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2658 +instret:513 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2658 +instret:514 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2659 +instret:515 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2659 +instret:516 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2660 +instret:517 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2660 +instret:518 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2661 +instret:519 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2661 +instret:520 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2662 + 26630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:521 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2663 +instret:522 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2663 + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:523 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2664 +instret:524 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2664 + 26650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:525 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2665 +instret:526 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2665 + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:527 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2666 +instret:528 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2666 + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:529 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2667 +instret:530 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2667 + 26680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:531 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2668 +instret:532 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2668 + 26690 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008240, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:533 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2669 +instret:534 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2669 +instret:535 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2670 + 26710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800081d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:536 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2671 +instret:537 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2671 + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800081d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800081d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:538 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2672 +instret:539 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2672 + 26730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:540 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2673 +instret:541 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2673 + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800081d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:542 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2674 +instret:543 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2674 +instret:544 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2675 +instret:545 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2675 +instret:546 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2676 +instret:547 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2676 +instret:548 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2677 +instret:549 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2677 +instret:550 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2678 + 26790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:551 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2679 +instret:552 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2679 + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800081e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:553 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2680 +instret:554 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2680 + 26810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:555 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2681 +instret:556 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2681 + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800081e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:557 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2682 +instret:558 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2682 +instret:559 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2683 +instret:560 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2683 +instret:561 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2684 +instret:562 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2684 + 26850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008200, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:563 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2685 +instret:564 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2685 + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:565 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2686 + 26870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:566 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2687 +instret:567 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2687 + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800081f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:568 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2688 +instret:569 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2688 + 26890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:570 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2689 +instret:571 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2689 + 26900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800081f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:572 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2690 +instret:573 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2690 +instret:574 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2691 +instret:575 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2691 +instret:576 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2692 +instret:577 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2692 +instret:578 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2693 +instret:579 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2693 +instret:580 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2694 + 26950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:581 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2695 +instret:582 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2695 + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 26960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:583 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2696 +instret:584 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2696 + 26970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:585 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2697 +instret:586 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2697 + 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 26980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 26980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:587 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2698 +instret:588 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2698 + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 26990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:589 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2699 +instret:590 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2699 + 27000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:591 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2700 +instret:592 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2700 + 27010 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008280, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:593 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2701 +instret:594 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2701 +instret:595 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2702 + 27030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:596 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2703 +instret:597 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2703 + 27040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:598 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2704 +instret:599 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2704 + 27050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:600 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2705 +instret:601 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2705 + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:602 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2706 +instret:603 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2706 +instret:604 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2707 +instret:605 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2707 +instret:606 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2708 +instret:607 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2708 +instret:608 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2709 +instret:609 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2709 +instret:610 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2710 + 27110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:611 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2711 +instret:612 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2711 + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:613 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2712 +instret:614 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2712 + 27130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:615 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2713 +instret:616 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2713 + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:617 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2714 +instret:618 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2714 +instret:619 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2715 +instret:620 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2715 +instret:621 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2716 +instret:622 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2716 + 27170 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008240, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:623 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2717 +instret:624 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2717 + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:625 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2718 + 27190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:626 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2719 +instret:627 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2719 + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:628 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2720 +instret:629 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2720 + 27210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:630 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2721 +instret:631 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2721 + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:632 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2722 +instret:633 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2722 +instret:634 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2723 +instret:635 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2723 +instret:636 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2724 +instret:637 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2724 +instret:638 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2725 +instret:639 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2725 +instret:640 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2726 + 27270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:641 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2727 +instret:642 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2727 + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:643 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2728 +instret:644 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2728 + 27290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:645 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2729 +instret:646 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2729 + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800082c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:647 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2730 +instret:648 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2730 + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800082c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:649 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2731 +instret:650 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2731 + 27320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800082c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:651 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2732 +instret:652 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2732 + 27330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800082c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800082c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 27330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800082c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:653 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2733 +instret:654 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2733 +instret:655 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2734 + 27350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:656 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2735 +instret:657 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2735 + 27360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:658 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2736 +instret:659 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2736 + 27370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:660 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2737 +instret:661 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2737 + 27380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:662 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2738 +instret:663 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2738 +instret:664 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2739 +instret:665 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2739 +instret:666 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2740 +instret:667 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2740 +instret:668 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2741 +instret:669 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2741 +instret:670 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2742 + 27430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:671 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2743 +instret:672 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2743 + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:673 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2744 +instret:674 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2744 + 27450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:675 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2745 +instret:676 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2745 + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:677 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2746 +instret:678 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2746 +instret:679 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2747 +instret:680 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2747 +instret:681 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2748 +instret:682 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2748 + 27490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008280, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:683 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2749 +instret:684 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2749 + 27500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 27500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:685 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2750 + 27510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:686 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2751 +instret:687 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2751 + 27520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:688 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2752 +instret:689 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2752 + 27530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:690 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2753 +instret:691 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2753 + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:692 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2754 +instret:693 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2754 +instret:694 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2755 +instret:695 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2755 +instret:696 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2756 +instret:697 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2756 +instret:698 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2757 +instret:699 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2757 +instret:700 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2758 + 27590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:701 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2759 +instret:702 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2759 + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:703 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2760 +instret:704 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2760 + 27610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:705 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2761 +instret:706 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2761 + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:707 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2762 +instret:708 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2762 + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:709 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2763 +instret:710 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2763 + 27640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:711 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2764 +instret:712 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2764 + 27650 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008300, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +instret:713 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2765 +instret:714 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2765 +instret:715 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2766 + 27670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:716 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2767 +instret:717 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2767 + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:718 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2768 +instret:719 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2768 + 27690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:720 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2769 +instret:721 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2769 + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:722 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2770 +instret:723 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2770 +instret:724 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2771 +instret:725 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2771 +instret:726 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2772 +instret:727 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2772 +instret:728 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2773 +instret:729 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2773 +instret:730 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2774 + 27750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800082a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:731 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2775 +instret:732 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2775 + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800082a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800082a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:733 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2776 +instret:734 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2776 + 27770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:735 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2777 +instret:736 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2777 + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:737 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2778 +instret:738 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2778 +instret:739 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2779 +instret:740 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2779 +instret:741 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2780 +instret:742 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2780 + 27810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800082c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:743 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2781 +instret:744 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2781 + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800082c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:745 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2782 + 27830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:746 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2783 +instret:747 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2783 + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:748 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2784 +instret:749 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2784 + 27850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:750 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2785 +instret:751 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2785 + 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:752 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2786 +instret:753 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2786 +instret:754 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2787 +instret:755 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2787 +instret:756 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2788 +instret:757 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2788 +instret:758 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2789 +instret:759 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2789 +instret:760 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2790 + 27910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:761 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2791 +instret:762 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2791 + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 27920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:763 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2792 +instret:764 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2792 + 27930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:765 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2793 +instret:766 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2793 + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 27940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 27940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:767 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2794 +instret:768 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2794 + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:769 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2795 +instret:770 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2795 + 27960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:771 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2796 +instret:772 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2796 + 27970 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008340, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 27970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +instret:773 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2797 +instret:774 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2797 +instret:775 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2798 + 27990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800082d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:776 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2799 +instret:777 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2799 + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800082d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800082d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:778 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2800 +instret:779 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2800 + 28010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:780 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2801 +instret:781 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2801 + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800082d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:782 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2802 +instret:783 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2802 +instret:784 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2803 +instret:785 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2803 +instret:786 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2804 +instret:787 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2804 +instret:788 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2805 +instret:789 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2805 +instret:790 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2806 + 28070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:791 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2807 +instret:792 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2807 + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800082e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:793 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2808 +instret:794 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2808 + 28090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:795 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2809 +instret:796 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2809 + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800082e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:797 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2810 +instret:798 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2810 +instret:799 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2811 +instret:800 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2811 +instret:801 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2812 +instret:802 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2812 + 28130 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008300, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:803 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2813 +instret:804 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2813 + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:805 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2814 + 28150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:806 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2815 +instret:807 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2815 + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800082f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:808 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2816 +instret:809 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2816 + 28170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:810 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2817 +instret:811 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2817 + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800082f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:812 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2818 +instret:813 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2818 +instret:814 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2819 +instret:815 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2819 +instret:816 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2820 +instret:817 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2820 +instret:818 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2821 +instret:819 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2821 +instret:820 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2822 + 28230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:821 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2823 +instret:822 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2823 + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:823 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2824 +instret:824 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2824 + 28250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:825 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2825 +instret:826 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2825 + 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:827 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2826 +instret:828 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2826 + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:829 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2827 +instret:830 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2827 + 28280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:831 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2828 +instret:832 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2828 + 28290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008380, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:833 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2829 +instret:834 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2829 +instret:835 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2830 + 28310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:836 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2831 +instret:837 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2831 + 28320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:838 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2832 +instret:839 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2832 + 28330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:840 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2833 +instret:841 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2833 + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:842 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2834 +instret:843 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2834 +instret:844 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2835 +instret:845 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2835 +instret:846 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2836 +instret:847 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2836 +instret:848 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2837 +instret:849 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2837 +instret:850 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2838 + 28390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:851 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2839 +instret:852 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2839 + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:853 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2840 +instret:854 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2840 + 28410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:855 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2841 +instret:856 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2841 + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:857 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2842 +instret:858 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2842 +instret:859 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2843 +instret:860 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2843 +instret:861 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2844 +instret:862 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2844 + 28450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008340, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:863 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2845 +instret:864 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2845 + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:865 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2846 + 28470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:866 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2847 +instret:867 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2847 + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:868 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2848 +instret:869 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2848 + 28490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:870 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2849 +instret:871 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2849 + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:872 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2850 +instret:873 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2850 +instret:874 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2851 +instret:875 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2851 +instret:876 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2852 +instret:877 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2852 +instret:878 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2853 +instret:879 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2853 +instret:880 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2854 + 28550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:881 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2855 +instret:882 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2855 + 28560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:883 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2856 +instret:884 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2856 + 28570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:885 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2857 +instret:886 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2857 + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800083c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:887 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2858 +instret:888 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2858 + 28590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800083c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:889 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2859 +instret:890 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2859 + 28600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800083c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:891 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2860 +instret:892 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2860 + 28610 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800083c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800083c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800083c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:893 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2861 +instret:894 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2861 +instret:895 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2862 + 28630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:896 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2863 +instret:897 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2863 + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:898 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2864 +instret:899 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2864 + 28650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:900 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2865 +instret:901 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2865 + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:902 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2866 +instret:903 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2866 +instret:904 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2867 +instret:905 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2867 +instret:906 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2868 +instret:907 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2868 +instret:908 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2869 +instret:909 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2869 +instret:910 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2870 + 28710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:911 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2871 +instret:912 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2871 + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080008360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:913 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2872 +instret:914 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2872 + 28730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:915 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2873 +instret:916 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2873 + 28740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:917 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2874 +instret:918 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2874 +instret:919 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2875 +instret:920 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2875 +instret:921 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2876 +instret:922 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2876 + 28770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008380, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:923 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2877 +instret:924 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2877 + 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:925 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2878 + 28790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:926 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2879 +instret:927 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2879 + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:928 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2880 +instret:929 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2880 + 28810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:930 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2881 +instret:931 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2881 + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:932 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2882 +instret:933 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2882 +instret:934 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2883 +instret:935 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2883 +instret:936 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2884 +instret:937 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2884 +instret:938 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2885 +instret:939 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2885 +instret:940 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2886 + 28870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:941 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2887 +instret:942 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2887 + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080008380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:943 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2888 +instret:944 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2888 + 28890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:945 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2889 +instret:946 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2889 + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080008388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 28900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:947 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2890 +instret:948 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2890 + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:949 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2891 +instret:950 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2891 + 28920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:951 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2892 +instret:952 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2892 + 28930 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008400, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 28930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:953 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2893 +instret:954 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2893 +instret:955 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2894 + 28950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:956 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2895 +instret:957 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2895 + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080008390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 28960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:958 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2896 +instret:959 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2896 + 28970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:960 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2897 +instret:961 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2897 + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080008398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 28980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:962 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2898 +instret:963 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2898 +instret:964 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2899 +instret:965 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2899 +instret:966 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2900 +instret:967 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2900 +instret:968 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2901 +instret:969 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2901 +instret:970 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2902 + 29030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800083a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:971 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2903 +instret:972 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2903 + 29040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800083a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800083a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:973 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2904 +instret:974 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2904 + 29050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800083a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:975 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2905 +instret:976 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2905 + 29060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800083a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800083a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:977 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2906 +instret:978 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2906 +instret:979 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2907 +instret:980 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2907 +instret:981 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2908 +instret:982 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2908 + 29090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800083c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:983 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2909 +instret:984 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2909 + 29100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 29100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800083c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 29100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:985 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2910 + 29110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:986 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2911 +instret:987 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2911 + 29120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:988 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2912 +instret:989 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2912 + 29130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:990 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2913 +instret:991 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2913 + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:992 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2914 +instret:993 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2914 +instret:994 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2915 +instret:995 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2915 +instret:996 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2916 +instret:997 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2916 +instret:998 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2917 +instret:999 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2917 +instret:1000 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2918 + 29190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:1001 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2919 +instret:1002 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2919 + 29200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1003 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2920 +instret:1004 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2920 + 29210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:1005 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2921 +instret:1006 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2921 + 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1007 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2922 +instret:1008 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2922 + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 29230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:1009 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2923 +instret:1010 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2923 + 29240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1011 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2924 +instret:1012 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2924 + 29250 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008440, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 29250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:1013 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2925 +instret:1014 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2925 +instret:1015 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2926 + 29270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800083d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:1016 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2927 +instret:1017 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2927 + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800083d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800083d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1018 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2928 +instret:1019 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2928 + 29290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:1020 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2929 +instret:1021 PC:0x1ffff0000000000000000000080002a00 instr:0x03f7871b iType:Alu [doCommitNormalInst [1]] 2929 + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800083d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1022 PC:0x1ffff0000000000000000000080002a04 instr:0x02071713 iType:Alu [doCommitNormalInst [0]] 2930 +instret:1023 PC:0x1ffff0000000000000000000080002a08 instr:0x0017d61b iType:Alu [doCommitNormalInst [1]] 2930 +instret:1024 PC:0x1ffff0000000000000000000080002a0c instr:0x02075713 iType:Alu [doCommitNormalInst [0]] 2931 +instret:1025 PC:0x1ffff0000000000000000000080002a10 instr:0x00c7c7b3 iType:Alu [doCommitNormalInst [1]] 2931 +instret:1026 PC:0x1ffff0000000000000000000080002a14 instr:0x01170733 iType:Alu [doCommitNormalInst [0]] 2932 +instret:1027 PC:0x1ffff0000000000000000000080002a18 instr:0x010685b3 iType:Alu [doCommitNormalInst [1]] 2932 +instret:1028 PC:0x1ffff0000000000000000000080002a1c instr:0x00c71713 iType:Alu [doCommitNormalInst [0]] 2933 +instret:1029 PC:0x1ffff0000000000000000000080002a20 instr:0x0057979b iType:Alu [doCommitNormalInst [1]] 2933 +instret:1030 PC:0x1ffff0000000000000000000080002a24 instr:0x00e6b023 iType:St [doCommitNormalInst [0]] 2934 + 29350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } +instret:1031 PC:0x1ffff0000000000000000000080002a28 instr:0x00b6b423 iType:St [doCommitNormalInst [0]] 2935 +instret:1032 PC:0x1ffff0000000000000000000080002a2c instr:0x0207f793 iType:Alu [doCommitNormalInst [1]] 2935 + 29370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa24 } + 29370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1033 PC:0x1ffff0000000000000000000080002a30 instr:0x01068693 iType:Alu [doCommitNormalInst [0]] 2937 +instret:1034 PC:0x1ffff0000000000000000000080002a34 instr:0x00c7e7b3 iType:Alu [doCommitNormalInst [1]] 2937 + 29380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } +instret:1035 PC:0x1ffff0000000000000000000080002a38 instr:0xfcd314e3 iType:Br [doCommitNormalInst [0]] 2938 + 29390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa28 } + 29390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008400, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 29420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1036 PC:0x1ffff0000000000000000000080002a3c instr:0x00050413 iType:Alu [doCommitNormalInst [0]] 2945 +instret:1037 PC:0x1ffff0000000000000000000080002a40 instr:0x12000613 iType:Alu [doCommitNormalInst [0]] 2946 +instret:1038 PC:0x1ffff0000000000000000000080002a44 instr:0x00000593 iType:Alu [doCommitNormalInst [1]] 2946 +instret:1039 PC:0x1ffff0000000000000000000080002a48 instr:0x00010513 iType:Alu [doCommitNormalInst [0]] 2947 +instret:1040 PC:0x1ffff0000000000000000000080002a4c instr:0x00006797 iType:Auipc [doCommitNormalInst [1]] 2947 +instret:1041 PC:0x1ffff0000000000000000000080002a50 instr:0x9807be23 iType:St [doCommitNormalInst [0]] 2948 +instret:1042 PC:0x1ffff0000000000000000000080002a54 instr:0xe08ff0ef iType:J [doCommitNormalInst [1]] 2948 + 29490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa50 } + 29500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa50 } + 29500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 29500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa50 } + 29500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 29730 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008440, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 29740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 29740 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 29740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 29740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1043 PC:0x1ffff000000000000000000008000205c instr:0x00c567b3 iType:Alu [doCommitNormalInst [0]] 3012 +instret:1044 PC:0x1ffff0000000000000000000080002060 instr:0x0077f793 iType:Alu [doCommitNormalInst [0]] 3013 +instret:1045 PC:0x1ffff0000000000000000000080002064 instr:0x00c50633 iType:Alu [doCommitNormalInst [1]] 3013 +instret:1046 PC:0x1ffff0000000000000000000080002068 instr:0x0ff5f593 iType:Alu [doCommitNormalInst [0]] 3015 +instret:1047 PC:0x1ffff000000000000000000008000206c instr:0x00078e63 iType:Br [doCommitNormalInst [1]] 3015 +instret:1048 PC:0x1ffff0000000000000000000080002088 instr:0x00859793 iType:Alu [doCommitNormalInst [0]] 3070 +instret:1049 PC:0x1ffff000000000000000000008000208c instr:0x00b7e5b3 iType:Alu [doCommitNormalInst [0]] 3071 +instret:1050 PC:0x1ffff0000000000000000000080002090 instr:0x01059793 iType:Alu [doCommitNormalInst [0]] 3072 +instret:1051 PC:0x1ffff0000000000000000000080002094 instr:0x00b7e7b3 iType:Alu [doCommitNormalInst [0]] 3073 +instret:1052 PC:0x1ffff0000000000000000000080002098 instr:0x02079593 iType:Alu [doCommitNormalInst [0]] 3074 +instret:1053 PC:0x1ffff000000000000000000008000209c instr:0x00f5e5b3 iType:Alu [doCommitNormalInst [0]] 3075 +instret:1054 PC:0x1ffff00000000000000000000800020a0 instr:0xfec572e3 iType:Br [doCommitNormalInst [1]] 3075 +instret:1055 PC:0x1ffff00000000000000000000800020a4 instr:0x00050793 iType:Alu [doCommitNormalInst [0]] 3077 +instret:1056 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 3077 +instret:1057 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3078 +instret:1058 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3078 + 30790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800095a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800095a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 30800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 30820 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800095a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800095a0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:1059 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3130 +instret:1060 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3132 +instret:1061 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3132 +instret:1062 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3140 +instret:1063 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3142 +instret:1064 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3142 +instret:1065 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3150 + 31510 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800095a0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800095a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1066 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3152 +instret:1067 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3152 + 31530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 31580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 31580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800095f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800095f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 31590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 31590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009630, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 31600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009630, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 31600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:1068 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3160 + 31610 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800095f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800095f0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 31620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009630, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009630, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:1069 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3162 +instret:1070 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3162 + 31630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 31640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1071 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3170 +instret:1072 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3172 +instret:1073 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3172 +instret:1074 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3180 +instret:1075 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3182 +instret:1076 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3182 +instret:1077 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3190 +instret:1078 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3192 +instret:1079 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3192 +instret:1080 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3200 +instret:1081 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3202 +instret:1082 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3202 + 32090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800095f0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800095f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:1083 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3210 + 32110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 32110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1084 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3211 +instret:1085 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3211 + 32120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1086 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3212 + 32130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080009640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1087 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3213 +instret:1088 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3213 + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080009640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 32140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1089 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3214 + 32150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800095d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1090 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3215 +instret:1091 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3215 + 32160 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080009640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009640, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 32160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1092 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3216 + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800095d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1093 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3217 +instret:1094 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3217 + 32180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1095 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3218 + 32190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800095e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1096 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3219 +instret:1097 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3219 + 32200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800095e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1098 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3220 + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800095e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800095e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1099 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3221 +instret:1100 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3221 + 32220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1101 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3222 + 32230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800095f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1102 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3223 +instret:1103 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3223 + 32240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1104 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3224 + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800095f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1105 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3225 +instret:1106 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3225 + 32260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1107 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3226 + 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:1108 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3227 +instret:1109 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3227 +instret:1110 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3228 +instret:1111 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3229 +instret:1112 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3229 +instret:1113 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3230 +instret:1114 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3231 +instret:1115 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3231 +instret:1116 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3232 +instret:1117 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3233 +instret:1118 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3233 +instret:1119 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3234 +instret:1120 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3235 +instret:1121 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3235 +instret:1122 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3236 +instret:1123 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3237 +instret:1124 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3237 +instret:1125 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3238 +instret:1126 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3239 +instret:1127 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3239 + 32400 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009630, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:1128 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3240 + 32410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 32410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009630, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +instret:1129 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3241 +instret:1130 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3241 + 32420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 32420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1131 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3242 + 32430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1132 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3243 +instret:1133 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3243 + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080009680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1134 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3244 + 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080009680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 32450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32470 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080009680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009680, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 32470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1135 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3248 +instret:1136 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3248 + 32490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1137 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3249 + 32500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1138 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3250 +instret:1139 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3250 + 32510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1140 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3251 + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1141 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3252 +instret:1142 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3252 + 32530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1143 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3253 + 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1144 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3254 +instret:1145 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3254 + 32550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1146 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3255 + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1147 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3256 +instret:1148 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3256 + 32570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1149 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3257 + 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +instret:1150 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3258 +instret:1151 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3258 +instret:1152 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3259 +instret:1153 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3260 +instret:1154 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3260 +instret:1155 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3261 +instret:1156 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3262 +instret:1157 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3262 +instret:1158 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3263 + 32710 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009640, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080009640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800096c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 32760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800096c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800096c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 32760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1159 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3279 +instret:1160 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3279 + 32800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } +instret:1161 PC:0x1ffff00000000000000000000800020a8 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 3280 + 32820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1162 PC:0x1ffff00000000000000000000800020ac instr:0xfeb7bc23 iType:St [doCommitNormalInst [0]] 3282 +instret:1163 PC:0x1ffff00000000000000000000800020b0 instr:0xfec7ece3 iType:Br [doCommitNormalInst [1]] 3282 + 32830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 32890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 32900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +instret:1164 PC:0x1ffff00000000000000000000800020b4 instr:0x00008067 iType:Jr [doCommitNormalInst [0]] 3290 +instret:1165 PC:0x1ffff0000000000000000000080002a58 instr:0x800007b7 iType:Alu [doCommitNormalInst [0]] 3291 +instret:1166 PC:0x1ffff0000000000000000000080002a5c instr:0x00f40433 iType:Alu [doCommitNormalInst [0]] 3292 +instret:1167 PC:0x1ffff0000000000000000000080002a60 instr:0x00010513 iType:Alu [doCommitNormalInst [0]] 3293 +instret:1168 PC:0x1ffff0000000000000000000080002a64 instr:0x10813423 iType:St [doCommitNormalInst [1]] 3293 +instret:1169 PC:0x1ffff0000000000000000000080002a68 instr:0xdd8fd0ef iType:J [doCommitNormalInst [0]] 3294 +instret:1170 PC:0x1ffff0000000000000000000080000040 instr:0x10853283 iType:Ld [doCommitNormalInst [0]] 3300 + 33020 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009680, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080009680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 33030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080009700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080009700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 33070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 33070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33090 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080009700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009700, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 33090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'ha0ac } + 33180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa64 } + 33200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa64 } + 33200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'haa64 } + 33200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1171 PC:0x1ffff0000000000000000000080000044 instr:0x14129073 iType:Scr [doCommitSystemInst] 3321 + 33320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800095a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8048 } + 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800095a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8048 } + 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800095a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8048 } + 33330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800095b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804c } + 33340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800095b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804c } + 33340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800095b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804c } + 33340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800095b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 } + 33350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800095b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 } + 33350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800095b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8050 } + 33350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800095c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 } + 33360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800095c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 } + 33360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800095c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8054 } + 33360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800095c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } +instret:1172 PC:0x1ffff0000000000000000000080000048 instr:0x00853083 iType:Ld [doCommitNormalInst [0]] 3336 + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800095c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800095c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8058 } + 33370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h00000000800095d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805c } +instret:1173 PC:0x1ffff000000000000000000008000004c instr:0x01053103 iType:Ld [doCommitNormalInst [0]] 3337 + 33380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h00000000800095d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805c } + 33380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h00000000800095d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805c } + 33380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800095d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } +instret:1174 PC:0x1ffff0000000000000000000080000050 instr:0x01853183 iType:Ld [doCommitNormalInst [0]] 3338 + 33390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800095d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + 33390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800095d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8060 } + 33390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h00000000800095e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 } +instret:1175 PC:0x1ffff0000000000000000000080000054 instr:0x02053203 iType:Ld [doCommitNormalInst [0]] 3339 + 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h00000000800095e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 } + 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h00000000800095e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 } + 33400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800095e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8068 } +instret:1176 PC:0x1ffff0000000000000000000080000058 instr:0x02853283 iType:Ld [doCommitNormalInst [0]] 3340 + 33410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800095e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8068 } + 33410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800095e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8068 } + 33410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800095f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } +instret:1177 PC:0x1ffff000000000000000000008000005c instr:0x03053303 iType:Ld [doCommitNormalInst [0]] 3341 + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800095f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800095f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h806c } + 33420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080009600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8070 } +instret:1178 PC:0x1ffff0000000000000000000080000060 instr:0x03853383 iType:Ld [doCommitNormalInst [0]] 3342 + 33430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080009600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8070 } + 33430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080009600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8070 } + 33430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080009608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8074 } +instret:1179 PC:0x1ffff0000000000000000000080000064 instr:0x04053403 iType:Ld [doCommitNormalInst [0]] 3343 + 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080009608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8074 } + 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080009608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8074 } + 33440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080009610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8078 } +instret:1180 PC:0x1ffff0000000000000000000080000068 instr:0x04853483 iType:Ld [doCommitNormalInst [0]] 3344 + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080009610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8078 } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080009610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8078 } + 33450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080009618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } +instret:1181 PC:0x1ffff000000000000000000008000006c instr:0x05853583 iType:Ld [doCommitNormalInst [0]] 3345 + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080009618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080009618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h807c } + 33460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1182 PC:0x1ffff0000000000000000000080000070 instr:0x06053603 iType:Ld [doCommitNormalInst [0]] 3346 +instret:1183 PC:0x1ffff0000000000000000000080000074 instr:0x06853683 iType:Ld [doCommitNormalInst [0]] 3347 +instret:1184 PC:0x1ffff0000000000000000000080000078 instr:0x07053703 iType:Ld [doCommitNormalInst [0]] 3348 +instret:1185 PC:0x1ffff000000000000000000008000007c instr:0x07853783 iType:Ld [doCommitNormalInst [0]] 3349 + 33570 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009700, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 33580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33580 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 33580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080009700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 33580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080009620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8080 } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080009620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8080 } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080009620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8080 } + 33960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080009628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } + 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080009628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } + 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080009628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8084 } + 33970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080009630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080009630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080009630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8088 } + 33980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080009638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808c } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080009638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808c } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080009638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h808c } + 33990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 33990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080009640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } +instret:1186 PC:0x1ffff0000000000000000000080000080 instr:0x08053803 iType:Ld [doCommitNormalInst [0]] 3399 + 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080009640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080009640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8090 } + 34000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080009648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } +instret:1187 PC:0x1ffff0000000000000000000080000084 instr:0x08853883 iType:Ld [doCommitNormalInst [0]] 3400 + 34010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080009648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } + 34010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080009648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8094 } + 34010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080009650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } +instret:1188 PC:0x1ffff0000000000000000000080000088 instr:0x09053903 iType:Ld [doCommitNormalInst [0]] 3401 + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080009650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080009650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8098 } + 34020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080009658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } +instret:1189 PC:0x1ffff000000000000000000008000008c instr:0x09853983 iType:Ld [doCommitNormalInst [0]] 3402 + 34030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080009658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 34030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080009658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h809c } + 34030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } +instret:1190 PC:0x1ffff0000000000000000000080000090 instr:0x0a053a03 iType:Ld [doCommitNormalInst [0]] 3403 + 34040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } + 34040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a0 } + 34040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } +instret:1191 PC:0x1ffff0000000000000000000080000094 instr:0x0a853a83 iType:Ld [doCommitNormalInst [0]] 3404 + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a4 } + 34050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a8 } +instret:1192 PC:0x1ffff0000000000000000000080000098 instr:0x0b053b03 iType:Ld [doCommitNormalInst [0]] 3405 + 34060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a8 } + 34060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80a8 } + 34060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } +instret:1193 PC:0x1ffff000000000000000000008000009c instr:0x0b853b83 iType:Ld [doCommitNormalInst [0]] 3406 + 34070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 34070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80ac } + 34070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b0 } +instret:1194 PC:0x1ffff00000000000000000000800000a0 instr:0x0c053c03 iType:Ld [doCommitNormalInst [0]] 3407 + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b0 } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b0 } + 34080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b4 } +instret:1195 PC:0x1ffff00000000000000000000800000a4 instr:0x0c853c83 iType:Ld [doCommitNormalInst [0]] 3408 + 34090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b4 } + 34090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b4 } + 34090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } +instret:1196 PC:0x1ffff00000000000000000000800000a8 instr:0x0d053d03 iType:Ld [doCommitNormalInst [0]] 3409 + 34100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 34100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80b8 } + 34100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 34100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } +instret:1197 PC:0x1ffff00000000000000000000800000ac instr:0x0d853d83 iType:Ld [doCommitNormalInst [0]] 3410 + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80bc } + 34110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1198 PC:0x1ffff00000000000000000000800000b0 instr:0x0e053e03 iType:Ld [doCommitNormalInst [0]] 3411 +instret:1199 PC:0x1ffff00000000000000000000800000b4 instr:0x0e853e83 iType:Ld [doCommitNormalInst [0]] 3412 +instret:1200 PC:0x1ffff00000000000000000000800000b8 instr:0x0f053f03 iType:Ld [doCommitNormalInst [0]] 3413 +instret:1201 PC:0x1ffff00000000000000000000800000bc instr:0x0f853f83 iType:Ld [doCommitNormalInst [0]] 3414 + 34540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800095f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800095f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800095f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h80c0 } + 34550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1202 PC:0x1ffff00000000000000000000800000c0 instr:0x05053503 iType:Ld [doCommitNormalInst [0]] 3458 +instret:1203 PC:0x1ffff00000000000000000000800000c4 instr:0x10200073 iType:Sret [doCommitSystemInst] 3460 + 34750 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080004000, toState: S, child: } + 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080004000, toState: S, child: } + 34760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 34770 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080004000, toState: S, child: } ; CRsMsg { addr: 'h0000000080004000, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } + 34930 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080005000, toState: S, child: } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080005000, toState: S, child: } + 34940 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 34950 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080005000, toState: S, child: } ; CRsMsg { addr: 'h0000000080005000, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:1204 PC:0x1ffff0000000000000000000000002adc instr:0x00000000 iType:Unsupported [doCommitTrap] 3558 + 35740 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080004ff8, toState: S, child: } + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080004ff8, toState: S, child: } + 35750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 35760 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080004ff8, toState: S, child: } ; CRsMsg { addr: 'h0000000080004ff8, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } + 35920 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080006ff8, toState: S, child: } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080006ff8, toState: S, child: } + 35930 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 35940 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080006ff8, toState: S, child: } ; CRsMsg { addr: 'h0000000080006ff8, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:1205 PC:0x1ffff000000000000ffffffffffe000c8 instr:0x14011173 iType:Csr [doCommitSystemInst] 3613 +instret:1206 PC:0x1ffff000000000000ffffffffffe000cc instr:0x00113423 iType:St [doCommitNormalInst [0]] 3628 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 36290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } +instret:1207 PC:0x1ffff000000000000ffffffffffe000d0 instr:0x00313c23 iType:St [doCommitNormalInst [0]] 3629 + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 36300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09700, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1208 PC:0x1ffff000000000000ffffffffffe000d4 instr:0x02413023 iType:St [doCommitNormalInst [0]] 3630 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09708, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 36310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } +instret:1209 PC:0x1ffff000000000000ffffffffffe000d8 instr:0x02513423 iType:St [doCommitNormalInst [0]] 3631 + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 36320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09710, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1210 PC:0x1ffff000000000000ffffffffffe000dc instr:0x02613823 iType:St [doCommitNormalInst [0]] 3632 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09718, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 36330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } +instret:1211 PC:0x1ffff000000000000ffffffffffe000e0 instr:0x02713c23 iType:St [doCommitNormalInst [0]] 3633 + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 36340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1212 PC:0x1ffff000000000000ffffffffffe000e4 instr:0x04813023 iType:St [doCommitNormalInst [0]] 3634 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09728, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 36350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } +instret:1213 PC:0x1ffff000000000000ffffffffffe000e8 instr:0x04913423 iType:St [doCommitNormalInst [0]] 3635 + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 36360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09730, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1214 PC:0x1ffff000000000000ffffffffffe000ec instr:0x04a13823 iType:St [doCommitNormalInst [0]] 3636 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09738, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 36370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } +instret:1215 PC:0x1ffff000000000000ffffffffffe000f0 instr:0x04b13c23 iType:St [doCommitNormalInst [0]] 3637 + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 36380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09740, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1216 PC:0x1ffff000000000000ffffffffffe000f4 instr:0x06c13023 iType:St [doCommitNormalInst [0]] 3638 + 36390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } +instret:1217 PC:0x1ffff000000000000ffffffffffe000f8 instr:0x06d13423 iType:St [doCommitNormalInst [0]] 3639 + 36400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 36400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 36400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1218 PC:0x1ffff000000000000ffffffffffe000fc instr:0x06e13823 iType:St [doCommitNormalInst [0]] 3640 + 36410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 36420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 36440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 36440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 36440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 36460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 36480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 36500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 36520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 36530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 36540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 36560 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009740, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09748, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09750, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09758, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1219 PC:0x1ffff000000000000ffffffffffe00100 instr:0x06f13c23 iType:St [doCommitNormalInst [0]] 3683 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09760, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1220 PC:0x1ffff000000000000ffffffffffe00104 instr:0x09013023 iType:St [doCommitNormalInst [0]] 3684 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09768, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1221 PC:0x1ffff000000000000ffffffffffe00108 instr:0x09113423 iType:St [doCommitNormalInst [0]] 3685 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09770, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1222 PC:0x1ffff000000000000ffffffffffe0010c instr:0x09213823 iType:St [doCommitNormalInst [0]] 3686 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09778, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1223 PC:0x1ffff000000000000ffffffffffe00110 instr:0x09313c23 iType:St [doCommitNormalInst [0]] 3687 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09780, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1224 PC:0x1ffff000000000000ffffffffffe00114 instr:0x0b413023 iType:St [doCommitNormalInst [0]] 3688 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09788, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1225 PC:0x1ffff000000000000ffffffffffe00118 instr:0x0b513423 iType:St [doCommitNormalInst [0]] 3689 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09790, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1226 PC:0x1ffff000000000000ffffffffffe0011c instr:0x0b613823 iType:St [doCommitNormalInst [0]] 3690 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09798, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1227 PC:0x1ffff000000000000ffffffffffe00120 instr:0x0b713c23 iType:St [doCommitNormalInst [0]] 3691 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1228 PC:0x1ffff000000000000ffffffffffe00124 instr:0x0d813023 iType:St [doCommitNormalInst [0]] 3692 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1229 PC:0x1ffff000000000000ffffffffffe00128 instr:0x0d913423 iType:St [doCommitNormalInst [0]] 3693 +instret:1230 PC:0x1ffff000000000000ffffffffffe0012c instr:0x0da13823 iType:St [doCommitNormalInst [0]] 3694 +instret:1231 PC:0x1ffff000000000000ffffffffffe00130 instr:0x0db13c23 iType:St [doCommitNormalInst [0]] 3695 + 37060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009740, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 37070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 37070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 37070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 37090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 37110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 37120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 37130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1232 PC:0x1ffff000000000000ffffffffffe00134 instr:0x0fc13023 iType:St [doCommitNormalInst [0]] 3713 + 37140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 37150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 37150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 37150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1233 PC:0x1ffff000000000000ffffffffffe00138 instr:0x0fd13423 iType:St [doCommitNormalInst [0]] 3715 + 37160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 37170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 37170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 37170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1234 PC:0x1ffff000000000000ffffffffffe0013c instr:0x0fe13823 iType:St [doCommitNormalInst [0]] 3717 + 37180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 37190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 37190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 37190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 37210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 37210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 37210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 37230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 37250 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080009780, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1235 PC:0x1ffff000000000000ffffffffffe00140 instr:0x0ff13c23 iType:St [doCommitNormalInst [0]] 3745 + 37730 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080009780, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 37740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37740 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 37740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 37740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 37760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 37780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 37780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 37780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 37800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 37820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 37820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 37820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 37840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 37860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 37880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 37890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 37900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 37920 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800097c0, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 38400 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800097c0, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 38410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 38410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 38410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 38410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 38420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 38430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 38430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 38430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 38430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 38430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1236 PC:0x1ffff000000000000ffffffffffe00144 instr:0x140112f3 iType:Csr [doCommitSystemInst] 3844 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1237 PC:0x1ffff000000000000ffffffffffe00148 instr:0x00513823 iType:St [doCommitNormalInst [0]] 3856 + 38570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 38580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 38580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 38580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 38580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 38580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1238 PC:0x1ffff000000000000ffffffffffe0014c instr:0x100022f3 iType:Csr [doCommitSystemInst] 3862 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1239 PC:0x1ffff000000000000ffffffffffe00150 instr:0x10513023 iType:St [doCommitNormalInst [0]] 4019 +instret:1240 PC:0x1ffff000000000000ffffffffffe00154 instr:0x141022f3 iType:Cap [doCommitNormalInst [1]] 4019 + 40200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } +instret:1241 PC:0x1ffff000000000000ffffffffffe00158 instr:0x10513423 iType:St [doCommitNormalInst [0]] 4020 + 40210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 40210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 40210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 40210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 40210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 40220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 40230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 40230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 40230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 40230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 40230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1242 PC:0x1ffff000000000000ffffffffffe0015c instr:0x143022f3 iType:Csr [doCommitSystemInst] 4026 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1243 PC:0x1ffff000000000000ffffffffffe00160 instr:0x10513823 iType:St [doCommitNormalInst [0]] 4080 + 40810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 40820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 40820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 40820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 40820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 40820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1244 PC:0x1ffff000000000000ffffffffffe00164 instr:0x142022f3 iType:Csr [doCommitSystemInst] 4086 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1245 PC:0x1ffff000000000000ffffffffffe00168 instr:0x10513c23 iType:St [doCommitNormalInst [0]] 4098 +instret:1246 PC:0x1ffff000000000000ffffffffffe0016c instr:0x00010513 iType:Alu [doCommitNormalInst [1]] 4098 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 40990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } +instret:1247 PC:0x1ffff000000000000ffffffffffe00170 instr:0x4380206f iType:J [doCommitNormalInst [0]] 4099 + 41000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 41000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 41000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1248 PC:0x1ffff000000000000ffffffffffe025a8 instr:0x11853583 iType:Ld [doCommitNormalInst [0]] 4102 +instret:1249 PC:0x1ffff000000000000ffffffffffe025ac instr:0xf9010113 iType:Alu [doCommitNormalInst [1]] 4102 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1250 PC:0x1ffff000000000000ffffffffffe025b0 instr:0x06813023 iType:St [doCommitNormalInst [0]] 4103 +instret:1251 PC:0x1ffff000000000000ffffffffffe025b4 instr:0x06113423 iType:St [doCommitNormalInst [1]] 4103 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 41040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } +instret:1252 PC:0x1ffff000000000000ffffffffffe025b8 instr:0x04913c23 iType:St [doCommitNormalInst [0]] 4104 +instret:1253 PC:0x1ffff000000000000ffffffffffe025bc instr:0x05213823 iType:St [doCommitNormalInst [1]] 4104 + 41050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 41050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 41050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09698, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1254 PC:0x1ffff000000000000ffffffffffe025c0 instr:0x05313423 iType:St [doCommitNormalInst [0]] 4105 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09690, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 41060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } +instret:1255 PC:0x1ffff000000000000ffffffffffe025c4 instr:0x05413023 iType:St [doCommitNormalInst [0]] 4106 + 41070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 41070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 41070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09688, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1256 PC:0x1ffff000000000000ffffffffffe025c8 instr:0x03513c23 iType:St [doCommitNormalInst [0]] 4107 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09680, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 41080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } +instret:1257 PC:0x1ffff000000000000ffffffffffe025cc instr:0x03613823 iType:St [doCommitNormalInst [0]] 4108 + 41090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 41090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 41090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09678, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1258 PC:0x1ffff000000000000ffffffffffe025d0 instr:0x03713423 iType:St [doCommitNormalInst [0]] 4109 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09670, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 41100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } +instret:1259 PC:0x1ffff000000000000ffffffffffe025d4 instr:0x03813023 iType:St [doCommitNormalInst [0]] 4110 + 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 41110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09668, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1260 PC:0x1ffff000000000000ffffffffffe025d8 instr:0x01913c23 iType:St [doCommitNormalInst [0]] 4111 + 41120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } +instret:1261 PC:0x1ffff000000000000ffffffffffe025dc instr:0x01a13823 iType:St [doCommitNormalInst [0]] 4112 + 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 41130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1262 PC:0x1ffff000000000000ffffffffffe025e0 instr:0x01b13423 iType:St [doCommitNormalInst [0]] 4113 +instret:1263 PC:0x1ffff000000000000ffffffffffe025e4 instr:0x00800793 iType:Alu [doCommitNormalInst [1]] 4113 + 41140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } +instret:1264 PC:0x1ffff000000000000ffffffffffe025e8 instr:0x00050413 iType:Alu [doCommitNormalInst [0]] 4114 +instret:1265 PC:0x1ffff000000000000ffffffffffe025ec instr:0x12f58a63 iType:Br [doCommitNormalInst [1]] 4114 + 41150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 41150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 41150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1266 PC:0x1ffff000000000000ffffffffffe025f0 instr:0x00200793 iType:Alu [doCommitNormalInst [0]] 4115 + 41160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } +instret:1267 PC:0x1ffff000000000000ffffffffffe025f4 instr:0x06f58063 iType:Br [doCommitNormalInst [0]] 4116 + 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 41170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1268 PC:0x1ffff000000000000ffffffffffe025f8 instr:0xff458793 iType:Alu [doCommitNormalInst [0]] 4117 +instret:1269 PC:0x1ffff000000000000ffffffffffe025fc instr:0x00100713 iType:Alu [doCommitNormalInst [1]] 4117 + 41180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 41190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 41190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 41190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 41200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 41210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 41210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 41210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 41220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 41230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 41230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 41230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 41240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 41250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 41250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 41250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 41260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 41270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 41280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 41290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1270 PC:0x1ffff000000000000ffffffffffe02600 instr:0x00f77663 iType:Br [doCommitNormalInst [0]] 4164 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 42200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } + 42210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 42210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } + 42210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 42210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } + 42210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1271 PC:0x1ffff000000000000ffffffffffe0260c instr:0x11043503 iType:Ld [doCommitNormalInst [0]] 4224 +instret:1272 PC:0x1ffff000000000000ffffffffffe02610 instr:0xcf9ff0ef iType:J [doCommitNormalInst [1]] 4224 +instret:1273 PC:0x1ffff000000000000ffffffffffe02308 instr:0xfffff6b7 iType:Alu [doCommitNormalInst [0]] 4225 +instret:1274 PC:0x1ffff000000000000ffffffffffe0230c instr:0x00d50733 iType:Alu [doCommitNormalInst [0]] 4226 +instret:1275 PC:0x1ffff000000000000ffffffffffe02310 instr:0x0003e7b7 iType:Alu [doCommitNormalInst [1]] 4226 +instret:1276 PC:0x1ffff000000000000ffffffffffe02314 instr:0x14f77463 iType:Br [doCommitNormalInst [0]] 4227 +instret:1277 PC:0x1ffff000000000000ffffffffffe02318 instr:0x00c55893 iType:Alu [doCommitNormalInst [1]] 4227 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1278 PC:0x1ffff000000000000ffffffffffe0231c instr:0x60088613 iType:Alu [doCommitNormalInst [0]] 4228 +instret:1279 PC:0x1ffff000000000000ffffffffffe02320 instr:0x00002817 iType:Auipc [doCommitNormalInst [1]] 4228 + 42290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } +instret:1280 PC:0x1ffff000000000000ffffffffffe02324 instr:0xce080813 iType:Alu [doCommitNormalInst [0]] 4229 +instret:1281 PC:0x1ffff000000000000ffffffffffe02328 instr:0x00361793 iType:Alu [doCommitNormalInst [1]] 4229 + 42300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 42300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } + 42300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:1282 PC:0x1ffff000000000000ffffffffffe0232c instr:0x00f807b3 iType:Alu [doCommitNormalInst [0]] 4230 + 42320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007010, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 43030 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007010, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } + 43040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1283 PC:0x1ffff000000000000ffffffffffe02330 instr:0x0007b703 iType:Ld [doCommitNormalInst [0]] 4307 +instret:1284 PC:0x1ffff000000000000ffffffffffe02334 instr:0x00d57533 iType:Alu [doCommitNormalInst [1]] 4307 +instret:1285 PC:0x1ffff000000000000ffffffffffe02338 instr:0x02070663 iType:Br [doCommitNormalInst [0]] 4310 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1286 PC:0x1ffff000000000000ffffffffffe02364 instr:0x00006797 iType:Auipc [doCommitNormalInst [0]] 4374 + 43750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800087e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc8c } +instret:1287 PC:0x1ffff000000000000ffffffffffe02368 instr:0x48478793 iType:Alu [doCommitNormalInst [0]] 4375 + 43760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 43760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800087e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc8c } + 43760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 43760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800087e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc8c } + 43760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08008, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1288 PC:0x1ffff000000000000ffffffffffe0236c instr:0x0007b703 iType:Ld [doCommitNormalInst [0]] 4379 + 43800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc94 } + 43810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 43810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc94 } + 43810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 43810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc94 } + 43810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1289 PC:0x1ffff000000000000ffffffffffe02370 instr:0x18070c63 iType:Br [doCommitNormalInst [0]] 4381 +instret:1290 PC:0x1ffff000000000000ffffffffffe02374 instr:0x00873783 iType:Ld [doCommitNormalInst [0]] 4384 +instret:1291 PC:0x1ffff000000000000ffffffffffe02378 instr:0x00006697 iType:Auipc [doCommitNormalInst [1]] 4384 +instret:1292 PC:0x1ffff000000000000ffffffffffe0237c instr:0x46868693 iType:Alu [doCommitNormalInst [0]] 4385 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 44280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc60 } + 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc60 } + 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc60 } + 44290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 44300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc70 } + 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc70 } + 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc70 } + 44310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1293 PC:0x1ffff000000000000ffffffffffe02380 instr:0x0006b683 iType:Ld [doCommitNormalInst [0]] 4432 +instret:1294 PC:0x1ffff000000000000ffffffffffe02384 instr:0x00006597 iType:Auipc [doCommitNormalInst [1]] 4432 +instret:1295 PC:0x1ffff000000000000ffffffffffe02388 instr:0x46f5b223 iType:St [doCommitNormalInst [0]] 4433 + 44340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc68 } +instret:1296 PC:0x1ffff000000000000ffffffffffe0238c instr:0x0cd78263 iType:Br [doCommitNormalInst [0]] 4434 +instret:1297 PC:0x1ffff000000000000ffffffffffe02390 instr:0x00073783 iType:Ld [doCommitNormalInst [1]] 4434 + 44350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 44350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc68 } + 44350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 44350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800087e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc68 } + 44350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1298 PC:0x1ffff000000000000ffffffffffe02394 instr:0x00361593 iType:Alu [doCommitNormalInst [0]] 4435 +instret:1299 PC:0x1ffff000000000000ffffffffffe02398 instr:0x00b805b3 iType:Alu [doCommitNormalInst [1]] 4435 +instret:1300 PC:0x1ffff000000000000ffffffffffe0239c instr:0x00c7d793 iType:Alu [doCommitNormalInst [0]] 4436 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1301 PC:0x1ffff000000000000ffffffffffe023a0 instr:0x00a79793 iType:Alu [doCommitNormalInst [0]] 4437 +instret:1302 PC:0x1ffff000000000000ffffffffffe023a4 instr:0x0df7e313 iType:Alu [doCommitNormalInst [0]] 4438 +instret:1303 PC:0x1ffff000000000000ffffffffffe023a8 instr:0x01f7e693 iType:Alu [doCommitNormalInst [0]] 4439 +instret:1304 PC:0x1ffff000000000000ffffffffffe023ac instr:0x0065b023 iType:St [doCommitNormalInst [1]] 4439 + 44400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc4c } + 44410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 44410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc4c } + 44410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 44410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc4c } + 44410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1305 PC:0x1ffff000000000000ffffffffffe023b0 instr:0x12050073 iType:SFence [doCommitSystemInst] 4442 +instret:1306 PC:0x1ffff000000000000ffffffffffe023b4 instr:0x00006797 iType:Auipc [doCommitNormalInst [0]] 4739 +instret:1307 PC:0x1ffff000000000000ffffffffffe023b8 instr:0x03c78793 iType:Alu [doCommitNormalInst [0]] 4740 +instret:1308 PC:0x1ffff000000000000ffffffffffe023bc instr:0x00489893 iType:Alu [doCommitNormalInst [1]] 4740 +instret:1309 PC:0x1ffff000000000000ffffffffffe023c0 instr:0x011788b3 iType:Alu [doCommitNormalInst [0]] 4741 + 47440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc24 } + 47450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 47450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc24 } + 47450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 47450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc24 } + 47450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 47450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc2c } + 47460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 47460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc2c } + 47460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 47460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080008000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc2c } + 47460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 47460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc34 } + 47470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 47470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc34 } + 47470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 47470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc34 } + 47470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1310 PC:0x1ffff000000000000ffffffffffe023c4 instr:0x0008b783 iType:Ld [doCommitNormalInst [0]] 4748 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08410, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08418, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1311 PC:0x1ffff000000000000ffffffffffe023c8 instr:0x18079863 iType:Br [doCommitNormalInst [0]] 4750 +instret:1312 PC:0x1ffff000000000000ffffffffffe023cc instr:0x00073783 iType:Ld [doCommitNormalInst [1]] 4750 +instret:1313 PC:0x1ffff000000000000ffffffffffe023d0 instr:0x00f8b023 iType:St [doCommitNormalInst [0]] 4751 + 47520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc30 } + 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc30 } + 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc30 } + 47530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1314 PC:0x1ffff000000000000ffffffffffe023d4 instr:0x00873783 iType:Ld [doCommitNormalInst [0]] 4753 +instret:1315 PC:0x1ffff000000000000ffffffffffe023d8 instr:0x00f8b423 iType:St [doCommitNormalInst [1]] 4753 + 47540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc38 } +instret:1316 PC:0x1ffff000000000000ffffffffffe023dc instr:0x000408b7 iType:Alu [doCommitNormalInst [0]] 4754 + 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc38 } + 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080008418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc38 } + 47550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1317 PC:0x1ffff000000000000ffffffffffe023e0 instr:0x1008a8f3 iType:Csr [doCommitSystemInst] 4760 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1318 PC:0x1ffff000000000000ffffffffffe023e4 instr:0xffe007b7 iType:Alu [doCommitNormalInst [0]] 4802 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02008, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 48030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1319 PC:0x1ffff000000000000ffffffffffe023e8 instr:0x00f507b3 iType:Alu [doCommitNormalInst [0]] 4803 +instret:1320 PC:0x1ffff000000000000ffffffffffe023ec instr:0x000015b7 iType:Alu [doCommitNormalInst [1]] 4803 + 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 48040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 48040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1321 PC:0x1ffff000000000000ffffffffffe023f0 instr:0x00050713 iType:Alu [doCommitNormalInst [0]] 4804 +instret:1322 PC:0x1ffff000000000000ffffffffffe023f4 instr:0x00b785b3 iType:Alu [doCommitNormalInst [1]] 4804 + 48050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 48050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02018, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 48050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 48060 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002000, fromState: I, toState: E, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 48060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 + 48060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 48070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 + 48540 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002000, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 48550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 48550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 48550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 48560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 48560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 48560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 48560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 48570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 48570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 48570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 48570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 48580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 48580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 48580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 48580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 48580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1323 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 4858 +instret:1324 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 4859 +instret:1325 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 4860 +instret:1326 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 4861 + 48870 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } + 48880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } + 48880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 48890 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } ; CRsMsg { addr: 'h0000000080007010, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:1327 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [0]] 4900 + 49010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1328 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 4901 + 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02020, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1329 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 4902 + 49040 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } ; L1CRqSlot { way: 'h3, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050000, fromState: I, toState: M, canUpToE: True, id: 'h3, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02028, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1330 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 4904 +instret:1331 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 4904 + 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02030, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1332 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 4905 +instret:1333 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 4905 + 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02038, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002020, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1334 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 4908 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002028, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1335 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 4909 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002030, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1336 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 4910 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002038, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1337 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 4911 +instret:1338 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 4911 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02040, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1339 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 4912 +instret:1340 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 4912 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02048, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1341 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 4913 +instret:1342 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 4913 + 49140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02050, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1343 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 4914 +instret:1344 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 4914 + 49150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02058, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49160 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002040, fromState: I, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 + 49160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 49170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002080, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002080, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 49180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 49200 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002080, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002080, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 49210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800020c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 49270 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002080, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02060, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49280 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800020c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002080, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02068, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 49290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02070, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02078, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h6 + 49310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49320 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002040, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 49320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 49340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 49340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 49360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002040, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1345 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 4936 + 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002048, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1346 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 4937 + 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002050, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1347 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 4938 + 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002058, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1348 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 4939 +instret:1349 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 4939 + 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002060, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002088, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1350 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 4940 +instret:1351 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 4940 + 49410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002088, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002088, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002068, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1352 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 4941 +instret:1353 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 4941 + 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1354 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 4942 +instret:1355 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 4942 + 49430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 49440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1356 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 4944 + 49450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800020b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1357 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 4945 + 49460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800020b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800020b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1358 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 4946 + 49470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800020f0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1359 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 4947 +instret:1360 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 4947 +instret:1361 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 4948 + 49520 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050000, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h3 } + 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050000, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050008, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002070, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050018, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002078, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1362 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 4959 + 49600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050020, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1363 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 4961 +instret:1364 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 4961 + 49620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050028, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 49630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:1365 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 4963 +instret:1366 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 4963 + 49640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050030, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 49650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050038, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 49670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 49680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 49690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 49710 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050040, fromState: I, toState: M, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02080, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02088, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02090, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02098, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49750 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002080, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 + 49750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 49760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 49770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 49770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 49790 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002100, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002080, toState: E, child: , data: tagged Invalid , id: 'h1 } + 49910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 49920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 49940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 49950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002080, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1367 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 4995 + 49960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 49960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 49960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002088, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1368 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 4996 + 49970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 49970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002090, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1369 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 4997 + 49980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 49980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002098, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1370 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 4998 +instret:1371 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 4998 + 49990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 49990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 49990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 49990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 49990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1372 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 4999 +instret:1373 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 4999 + 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1374 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5000 +instret:1375 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5000 + 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 50010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002118, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1376 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5001 +instret:1377 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5001 + 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002118, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:1378 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5003 +instret:1379 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5004 +instret:1380 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5005 +instret:1381 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5006 +instret:1382 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5006 +instret:1383 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5007 + 50190 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050040, toState: M, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050040, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050048, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050050, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050058, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1384 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5026 + 50270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 50270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050060, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800500d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1385 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5028 +instret:1386 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5028 + 50290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050090, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 50290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800500d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:1387 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5030 +instret:1388 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5030 + 50310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050068, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800500d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800500d0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 50320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050098, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 50320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050070, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50330 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 50340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050078, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800500a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800500a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 50360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 50370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800500e0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800500e0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50420 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800020c0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 50420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h4 + 50420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 + 50500 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002100, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800500e8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800500e8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 50540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002140, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50580 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800020c0, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50590 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 50590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 50600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 50610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 50620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 50620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1389 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5062 + 50630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 50630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1390 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5063 + 50640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 50640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1391 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5064 + 50650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 50650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1392 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5065 +instret:1393 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5065 + 50660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 50660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1394 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5066 +instret:1395 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5066 + 50670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1396 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5067 +instret:1397 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5067 + 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 50680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002158, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1398 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5068 +instret:1399 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5068 + 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002158, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:1400 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5070 +instret:1401 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5071 +instret:1402 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5072 +instret:1403 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5073 +instret:1404 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5073 +instret:1405 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5074 + 50810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050090, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 50820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 50820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050090, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 50830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 50830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050080, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050088, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 50860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050090, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50870 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 50880 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050100, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050108, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 50880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050098, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 50890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1406 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5089 + 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050110, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 50900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 50910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050118, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1407 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5091 +instret:1408 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5091 + 50920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050118, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 50930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +instret:1409 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5093 +instret:1410 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5093 + 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 50940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800500b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800500b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800500b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 50960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 50980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 50980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 50980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 50990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02100, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02108, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02110, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02118, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002100, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1411 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5106 + 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002108, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1412 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5107 + 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002110, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1413 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5108 + 51090 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002180, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002118, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002190, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1414 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5109 +instret:1415 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5109 + 51100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002190, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1416 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5110 +instret:1417 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5110 + 51110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002198, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 51120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800500d0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 51120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002198, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1418 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5112 +instret:1419 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5112 + 51130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 51130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800500d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:1420 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5113 +instret:1421 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5113 + 51140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800500c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 51170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 51170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02120, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 51190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050140, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 51190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050148, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02128, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02130, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02138, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002120, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1422 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5123 + 51240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002128, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1423 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5124 + 51250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050150, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002130, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1424 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5125 + 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800500e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002138, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050158, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1425 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5126 +instret:1426 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5126 + 51270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050158, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02140, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1427 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5127 +instret:1428 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5127 + 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800500e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02148, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1429 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5128 +instret:1430 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5128 + 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02150, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1431 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5129 +instret:1432 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5129 + 51300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02158, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 + 51310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02160, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02168, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02170, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51430 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002140, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 51440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 51440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 51450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 51450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 51480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002140, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1433 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5148 + 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002148, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1434 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5149 + 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002150, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1435 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5150 + 51510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002158, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1436 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5151 +instret:1437 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5151 + 51520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1438 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5152 +instret:1439 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5152 + 51530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002160, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1440 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5153 +instret:1441 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5153 + 51540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800500f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1442 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5154 +instret:1443 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5154 + 51550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 51550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 51560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1444 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5156 + 51570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800021c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 51570 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800021d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1445 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5157 + 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800021d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002168, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800021d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1446 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5158 + 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800021d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:1447 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5159 +instret:1448 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5159 +instret:1449 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5160 + 51740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050100, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 51750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 51750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 51760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 51760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050100, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050108, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 51780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 51780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 51790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050110, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 51800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002170, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51800 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 51810 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050180, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 51810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050118, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 51820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002178, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 51820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050190, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1450 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5182 + 51830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050190, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 51830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050120, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 51840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050198, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1451 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5184 +instret:1452 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5184 + 51850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050198, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 51850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02188, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1453 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5185 +instret:1454 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5185 + 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 51860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02190, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 51870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02198, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 51870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 51880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 + 51880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 51890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 + 52050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002180, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 52060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 52060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 52070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 52070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 52090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 52100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002180, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1455 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5210 + 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050128, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002188, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1456 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5211 + 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002190, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1457 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5212 + 52130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050130, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1458 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5213 +instret:1459 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5213 + 52140 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002200, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 52140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1460 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5214 +instret:1461 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5214 + 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050138, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002198, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52150 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002210, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 52160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002210, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 52160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002218, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1462 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5217 +instret:1463 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5217 + 52180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002218, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1464 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5218 +instret:1465 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5218 + 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1466 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5222 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1467 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5223 +instret:1468 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5224 +instret:1469 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5225 +instret:1470 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5225 +instret:1471 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5226 + 52360 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050140, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050140, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050148, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 52410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 52410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050150, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 52430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800501c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 52430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 52430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050158, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800501d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1472 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5244 + 52450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800501d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 52450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050160, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1473 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5246 +instret:1474 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5246 + 52470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1475 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5247 +instret:1476 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5247 + 52480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h4 + 52500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 + 52670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800021c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 52690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 52710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1477 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5272 + 52730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050168, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 52730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1478 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5273 + 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1479 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5274 + 52750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050170, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 52750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1480 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5275 +instret:1481 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5275 + 52760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002240, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 52760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1482 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5276 +instret:1483 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5276 + 52770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050178, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 52770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 52770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002250, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 52780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002250, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 52780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 52790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002258, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1484 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5279 +instret:1485 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5279 + 52800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002258, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1486 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5280 +instret:1487 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5280 + 52810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 52810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 52820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 52820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 52830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 52830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 52840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1488 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5284 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1489 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5285 +instret:1490 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5286 +instret:1491 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5287 +instret:1492 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5287 +instret:1493 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5288 + 52980 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050180, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 52990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 52990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 52990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 52990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 53000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050180, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 53030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050190, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 53050 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050200, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 53050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 53050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050198, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050210, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1494 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5306 + 53070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050210, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 53070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800501a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800501a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800501a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02200, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050218, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1495 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5308 +instret:1496 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5308 + 53090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050218, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02208, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1497 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5309 +instret:1498 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5309 + 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02210, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02218, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h7 + 53120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 53290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002200, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 53300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 53300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 53310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 53310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 53330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 53340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002200, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1499 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5334 + 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002208, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1500 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5335 + 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002210, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1501 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5336 + 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1502 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5337 +instret:1503 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5337 + 53380 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002280, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 53380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1504 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5338 +instret:1505 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5338 + 53390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002218, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002290, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002290, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 53400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02220, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002298, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1506 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5341 +instret:1507 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5341 + 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002298, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02228, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1508 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5342 +instret:1509 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5342 + 53430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02230, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02238, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002220, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1510 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5346 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002228, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1511 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5347 +instret:1512 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5348 +instret:1513 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5349 +instret:1514 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5349 +instret:1515 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5350 + 53600 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800501c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 53620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 53650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 53650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002230, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 53670 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050240, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 53670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050248, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 53670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800501d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 53680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002238, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050250, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1516 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5368 + 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050250, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 53690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800501e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 53700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02240, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050258, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1517 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5370 +instret:1518 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5370 + 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050258, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02248, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1519 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5371 +instret:1520 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5371 + 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02250, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02258, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 53730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 53740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 + 53910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002240, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 53920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 53920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 53930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 53930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 53940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 53950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 53960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 53960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 53960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002240, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1521 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5396 + 53970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 53970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002248, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1522 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5397 + 53980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 53980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002250, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 53980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1523 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5398 + 53990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 53990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 53990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800501f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 53990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 53990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800022c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1524 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5399 +instret:1525 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5399 + 54000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800022c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 54000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800022c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 54000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800501f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1526 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5400 +instret:1527 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5400 + 54010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800501f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800501f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002258, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800022d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800022d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 54020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02260, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800022d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1528 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5403 +instret:1529 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5403 + 54040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800022d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02268, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1530 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5404 +instret:1531 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5404 + 54050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02270, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02278, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002260, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1532 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5408 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002268, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1533 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5409 +instret:1534 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5410 +instret:1535 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5411 +instret:1536 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5411 +instret:1537 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5412 + 54220 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050200, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 54240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050200, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050208, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 54270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050210, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002270, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050280, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050288, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 54290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050218, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002278, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050290, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1538 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5430 + 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050290, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 54310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050220, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02280, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050298, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1539 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5432 +instret:1540 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5432 + 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050298, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02288, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1541 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5433 +instret:1542 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5433 + 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02290, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02298, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 + 54360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 + 54530 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002280, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 54540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 54540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 54550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 54570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 54580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002280, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1543 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5458 + 54590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050228, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002288, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1544 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5459 + 54600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002290, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1545 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5460 + 54610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050230, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1546 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5461 +instret:1547 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5461 + 54620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002300, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 54620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 54620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1548 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5462 +instret:1549 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5462 + 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050238, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002298, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002310, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002310, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 54640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002318, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1550 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5465 +instret:1551 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5465 + 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002318, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1552 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5466 +instret:1553 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5466 + 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54690 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002300, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 54690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1554 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5470 + 54710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1555 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5471 +instret:1556 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5472 +instret:1557 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5474 +instret:1558 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5474 +instret:1559 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5475 + 54840 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050240, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 54860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 54860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050240, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 54880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 54880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 54890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050250, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 54900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800502c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 54910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800502c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 54910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800502c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 54910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050258, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 54920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 54920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800502d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1560 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5492 + 54930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800502d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 54930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 54940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050260, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 54940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800502d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1561 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5494 +instret:1562 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5494 + 54950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800502d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 54950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1563 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5495 +instret:1564 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5495 + 54960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 54960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 54970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 54970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 54980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 54980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 54990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 54990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050268, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050270, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050278, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55150 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800022c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 55170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 55200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1565 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5520 + 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1566 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5521 + 55220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1567 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5522 + 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1568 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5523 +instret:1569 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5523 + 55240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1570 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5524 +instret:1571 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5524 + 55250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1572 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5525 +instret:1573 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5525 + 55260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 55260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002350, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1574 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5526 +instret:1575 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5526 + 55270 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002340, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 55270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002350, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 55270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002358, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 55280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002358, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1576 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5528 +instret:1577 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5529 +instret:1578 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5530 +instret:1579 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5531 +instret:1580 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5531 +instret:1581 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5532 + 55340 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002340, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 55350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55350 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55460 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050280, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 55470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050280, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050288, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 55510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050290, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 55530 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050300, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050308, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 55530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050298, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050310, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1582 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5554 + 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050310, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 55550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02300, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050318, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1583 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5556 +instret:1584 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5556 + 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050318, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02308, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1585 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5557 +instret:1586 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5557 + 55580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02310, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02318, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55600 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002300, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 55600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 55600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h4 + 55610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 55630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 55630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55650 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002380, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 55650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02320, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02328, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02330, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02338, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55720 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002380, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 55730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55730 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h2 + 55760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002300, toState: E, child: , data: tagged Invalid , id: 'h1 } + 55770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800502c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 55770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 55780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 55790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 55800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002300, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1587 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5580 + 55810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002308, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1588 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5581 + 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002310, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1589 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5582 + 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800502c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002318, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1590 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5583 +instret:1591 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5583 + 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002320, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1592 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5584 +instret:1593 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5584 + 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1594 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5585 +instret:1595 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5585 + 55860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1596 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5586 +instret:1597 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5586 + 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002328, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55870 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 55880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002330, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800502d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1598 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5588 + 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800502d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800502d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 55890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002390, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1599 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5589 + 55900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002390, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002390, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800502d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1600 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5590 + 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800502d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800502d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 55910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002338, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 55910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002398, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1601 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5591 +instret:1602 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5591 + 55920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002398, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002398, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800502e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1603 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5592 +instret:1604 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5592 + 55930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800502e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800502e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 55930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02340, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1605 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5593 +instret:1606 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5593 + 55940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 55940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02348, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1607 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5594 +instret:1608 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5594 + 55950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 55950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02350, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050340, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 55960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 55960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02358, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 55960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55970 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002340, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 55970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 55970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 55970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 55980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 55980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 55990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 55990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050348, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 56000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050350, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050350, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 56020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800502f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050358, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050358, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 56040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02360, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56050 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02368, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02370, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56080 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050300, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 56080 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800023c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02378, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56090 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 56100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050300, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 + 56110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 56130 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002340, toState: E, child: , data: tagged Invalid , id: 'h1 } + 56140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56140 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 56150 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800023c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 56150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002340, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1609 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5617 + 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002348, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1610 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5618 + 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002350, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1611 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5619 + 56200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002358, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1612 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5620 +instret:1613 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5620 + 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002360, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1614 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5621 +instret:1615 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5621 + 56220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002368, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1616 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5622 +instret:1617 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5622 + 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1618 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5623 +instret:1619 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5623 + 56240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002370, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050310, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800023c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1620 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5625 + 56260 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050380, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 56260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800023c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800023c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1621 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5626 + 56270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050318, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002378, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800023d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1622 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5627 + 56280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800023d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800023d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1623 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5628 +instret:1624 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5628 + 56290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050320, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02380, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800023d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1625 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5629 +instret:1626 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5629 + 56300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800023d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800023d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02388, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1627 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5630 +instret:1628 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5630 + 56310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02390, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1629 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5631 +instret:1630 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5631 + 56320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02398, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002380, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 56330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h4 + 56340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050328, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050388, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 56360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050330, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050390, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050390, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 56380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050338, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050398, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050398, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 56400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56440 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050340, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 56440 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002400, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56450 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 56460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050340, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 56470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 + 56490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002380, toState: E, child: , data: tagged Invalid , id: 'h1 } + 56500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 56510 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002400, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 56510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 56520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 56530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002380, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1631 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5653 + 56540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002388, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1632 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5654 + 56550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002390, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1633 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5655 + 56560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002398, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1634 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5656 +instret:1635 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5656 + 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1636 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5657 +instret:1637 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5657 + 56580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1638 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5658 +instret:1639 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5658 + 56590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050348, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1640 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5659 +instret:1641 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5659 + 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050350, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1642 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5661 + 56620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800503c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 56620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1643 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5662 + 56630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050358, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002410, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1644 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5663 + 56640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002410, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002410, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1645 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5664 +instret:1646 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5664 + 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050360, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002418, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1647 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5665 +instret:1648 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5665 + 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002418, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002418, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1649 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5666 +instret:1650 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5666 + 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1651 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5667 +instret:1652 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5667 + 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56690 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800023c0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 + 56690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h0 + 56700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800503c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800503c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 56720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050370, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800503d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800503d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 56740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56750 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050380, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 56750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050378, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050380, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 56770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800503d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800503d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 56800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 56850 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800023c0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 56860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56860 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 56860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 56870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 56870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1653 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5689 + 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 56900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1654 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5690 + 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 56910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1655 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5691 + 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 56920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1656 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5692 +instret:1657 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5692 + 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 56930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1658 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5693 +instret:1659 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5693 + 56940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050388, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 56940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1660 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5694 +instret:1661 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5694 + 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1662 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5695 +instret:1663 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5695 + 56960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050390, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 56960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 56960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 56970 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002440, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 56970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1664 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5697 + 56980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 56980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050398, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 56980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 56980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1665 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5698 + 56990 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050400, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 56990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 56990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800503a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1666 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5699 + 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800503a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800503a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02400, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002450, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1667 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5700 +instret:1668 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5700 + 57010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002450, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02408, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1669 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5701 +instret:1670 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5701 + 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02410, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1671 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5702 +instret:1672 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5702 + 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02418, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1673 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5703 +instret:1674 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5703 + 57040 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002440, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 57040 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002400, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 57040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h4 + 57050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57050 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 57060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002458, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002458, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002458, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57090 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h00000000800023f8, toState: S, child: } + 57090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57100 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800503c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h00000000800023f8, toState: S, child: } + 57100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 57110 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h00000000800023f8, toState: S, child: } ; CRsMsg { addr: 'h00000000800023f8, toState: S, data: tagged Invalid , child: } + 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050408, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 57130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050410, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050410, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 57150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050418, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050418, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 57170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 57190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57200 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002400, toState: E, child: , data: tagged Invalid , id: 'h1 } + 57200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800503d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002480, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 57210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 57230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 57240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002400, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1675 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5724 + 57250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800503e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002408, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1676 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5725 + 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002410, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1677 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5726 + 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 57270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002418, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1678 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5727 +instret:1679 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5727 + 57280 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002480, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 57280 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050440, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 57280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050448, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02420, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1680 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5728 +instret:1681 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5728 + 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02428, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800503f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1682 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5729 +instret:1683 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5729 + 57300 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080002408, toState: S, child: } + 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800503f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800503f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 57300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02430, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:1684 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5730 +instret:1685 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5730 + 57310 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080002408, toState: S, child: } + 57310 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02438, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57320 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080002408, toState: S, child: } ; CRsMsg { addr: 'h0000000080002408, toState: S, data: tagged Invalid , child: } + 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 57320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 57330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57340 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002420, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h0 + 57340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h7 + 57350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800503f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 57360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050450, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050450, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 57370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 57380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 57380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050458, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050458, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 57400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002488, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002488, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002488, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002490, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002490, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002490, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002498, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002498, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002498, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 57450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 57500 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002420, toState: E, child: , data: tagged Invalid , id: 'h1 } + 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 57520 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002418, toState: S, child: } + 57520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 57540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002420, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002418, toState: S, child: } + 57550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 57560 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002418, toState: S, child: } ; CRsMsg { addr: 'h0000000080002418, toState: S, data: tagged Invalid , child: } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02420, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02428, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02430, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02438, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57750 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002420, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 57750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 + 57750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02440, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02448, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02450, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02458, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002440, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02460, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02468, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002420, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02470, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 57920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 57920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02478, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 57930 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002410, toState: S, child: } + 57930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 57940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002420, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1686 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5795 + 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002410, toState: S, child: } + 57960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002428, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1687 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5796 + 57970 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002410, toState: S, child: } ; CRsMsg { addr: 'h0000000080002410, toState: S, data: tagged Invalid , child: } + 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 57970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002430, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1688 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5797 + 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 57980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002438, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 57980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1689 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5798 +instret:1690 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5798 + 57990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 57990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 57990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 57990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1691 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5799 +instret:1692 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5799 + 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +instret:1693 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5800 +instret:1694 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5800 + 58010 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002440, toState: E, child: , data: tagged Invalid , id: 'h1 } +instret:1695 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5801 +instret:1696 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5801 + 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 58030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 58030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 58050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002440, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1697 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5805 + 58060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002448, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1698 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5806 + 58070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002450, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1699 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5807 + 58080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002458, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1700 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5808 +instret:1701 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5808 + 58090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002460, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1702 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5809 +instret:1703 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5809 + 58100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002468, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1704 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5810 +instret:1705 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5810 + 58110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1706 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5811 +instret:1707 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5811 + 58120 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800024c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 58120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800024c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800024c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 58130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800024d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1708 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5813 + 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800024d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 58140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800024d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1709 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5814 + 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800024d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:1710 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5815 +instret:1711 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5816 +instret:1712 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5816 +instret:1713 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5817 + 58190 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800024c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 58200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 58200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58260 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050400, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 58270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 58270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 58280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050400, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050408, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 58310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002470, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050488, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050480, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 58330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050488, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 58330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050418, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002478, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050490, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1714 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5834 + 58350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050490, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 58350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050420, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02480, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050498, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1715 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5836 +instret:1716 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5836 + 58370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050498, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02488, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1717 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5837 +instret:1718 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5837 + 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02490, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02498, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002480, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 58400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h7 + 58400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h0 + 58410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 58430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050430, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58450 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002500, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 58450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050438, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58560 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002480, toState: E, child: , data: tagged Invalid , id: 'h0 } + 58570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58570 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 58570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 58580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 58580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 58600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002480, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1719 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5860 + 58610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002488, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1720 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5861 + 58620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002490, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1721 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5862 + 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002498, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1722 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5863 +instret:1723 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5863 + 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002508, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1724 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5864 +instret:1725 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5864 + 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002508, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002510, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1726 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5865 +instret:1727 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5865 + 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002510, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 58660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002518, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1728 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5866 +instret:1729 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5866 + 58670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002518, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1730 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5868 +instret:1731 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5869 +instret:1732 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5870 +instret:1733 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5871 +instret:1734 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5871 +instret:1735 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5872 + 58780 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050440, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 58790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 58790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050440, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050448, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 58830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050450, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800504c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 58850 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800504c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800504c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 58850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050458, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 58860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800504d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1736 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5886 + 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800504d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 58870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050460, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 58880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800504d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1737 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5888 +instret:1738 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5888 + 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800504d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 58890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1739 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5889 +instret:1740 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5889 + 58900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 58900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 58910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 58910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58920 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800024c0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 58920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 58920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 58920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 58930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 + 58930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050468, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 58940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050470, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 58960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 58980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 58980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050478, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 58980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 58990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59080 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800024c0, toState: E, child: , data: tagged Invalid , id: 'h0 } + 59090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050480, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 59090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59090 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 59090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 59100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 59110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1741 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5912 + 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1742 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5913 + 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050480, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1743 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5914 + 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1744 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5915 +instret:1745 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5915 + 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1746 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5916 +instret:1747 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5916 + 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1748 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5917 +instret:1749 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5917 + 59180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1750 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5918 +instret:1751 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5918 + 59190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59190 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 59200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1752 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5920 + 59210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050490, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002548, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1753 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5921 + 59220 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002540, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 59220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002548, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 59220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1754 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5922 + 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050498, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002550, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1755 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5923 +instret:1756 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5923 + 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002550, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 59240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800504a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1757 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5924 +instret:1758 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5924 + 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800504a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800504a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02500, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002558, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1759 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5925 +instret:1760 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5925 + 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002558, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02508, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1761 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5926 +instret:1762 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5926 + 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02510, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02518, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 + 59290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h5 + 59300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02520, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02528, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02530, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59400 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002500, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02538, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 59410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 59420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 59450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002500, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1763 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5945 + 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002508, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1764 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5946 + 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002510, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1765 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5947 + 59480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002518, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1766 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5948 +instret:1767 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5948 + 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002520, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1768 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5949 +instret:1769 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 5949 + 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002528, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050508, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1770 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5950 +instret:1771 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5950 + 59510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050508, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 59510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050510, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1772 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5951 +instret:1773 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5951 + 59520 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050500, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 59520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050510, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 59520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050518, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 59530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050518, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 59530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1774 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 5953 + 59540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 59540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002588, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1775 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 5954 + 59550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002588, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 59550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002590, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1776 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 5955 + 59560 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002580, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 59560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002590, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 59560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002598, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1777 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 5956 +instret:1778 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 5956 + 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002598, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +instret:1779 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 5957 + 59630 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002580, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59710 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800504c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 59720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59720 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 59720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800504c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 59760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002530, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050548, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 59780 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050540, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 59780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050548, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 59780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800504d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800504d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800504d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002538, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 59790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050550, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1780 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 5979 + 59800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050550, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 59800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800504e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02540, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59810 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050558, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1781 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 5981 +instret:1782 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 5981 + 59820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050558, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 59820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02548, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1783 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 5982 +instret:1784 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 5982 + 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 59830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02550, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 59840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02558, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 59840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 59850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 + 59850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 59860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 59860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 59870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 59890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 59910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 59920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 59930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02560, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02568, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02570, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02578, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60020 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002540, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 60030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60030 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 60040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 60040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 60060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 60070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002540, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1785 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6007 + 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002548, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1786 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6008 + 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002550, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1787 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6009 + 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002558, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1788 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6010 +instret:1789 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6010 + 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002560, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1790 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6011 +instret:1791 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6011 + 60120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002568, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800025c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1792 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6012 +instret:1793 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6012 + 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800025c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 60130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1794 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6013 +instret:1795 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6013 + 60140 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800025c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 60140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 60140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800025d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800025d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:1796 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6015 +instret:1797 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6016 +instret:1798 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6017 +instret:1799 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6018 +instret:1800 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6018 +instret:1801 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6019 + 60210 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800025c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 60220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60220 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60330 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050500, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 60350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050500, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050508, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 60380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050510, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002570, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050588, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60400 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050580, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 60400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050588, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 60400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050518, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002578, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050590, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1802 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6041 + 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050590, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 60420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050520, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02580, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050598, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1803 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6043 +instret:1804 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6043 + 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050598, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02588, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1805 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6044 +instret:1806 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6044 + 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02590, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02598, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60470 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002580, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h2 + 60470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h4 + 60480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050528, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 60500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050530, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60520 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002600, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 60520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050538, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60590 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002600, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 60630 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002580, toState: E, child: , data: tagged Invalid , id: 'h0 } + 60640 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050540, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 60650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 60670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002580, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1807 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6067 + 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002588, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1808 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6068 + 60690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60690 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002590, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1809 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6069 + 60700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050540, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002598, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1810 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6070 +instret:1811 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6070 + 60710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1812 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6071 +instret:1813 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6071 + 60720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1814 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6072 +instret:1815 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6072 + 60730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1816 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6073 +instret:1817 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6073 + 60740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60740 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002608, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002608, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002608, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1818 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6075 + 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050550, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002610, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1819 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6076 + 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002610, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002610, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1820 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6077 + 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050558, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 60780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002618, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1821 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6078 +instret:1822 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6078 + 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002618, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002618, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1823 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6079 +instret:1824 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6079 + 60800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050560, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60800 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1825 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6080 +instret:1826 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6080 + 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1827 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6081 +instret:1828 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6081 + 60820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60830 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800505c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800025c0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 60840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 60840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 60840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 60850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 + 60850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050568, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 60860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 60870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050570, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 60880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 60890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 60900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050578, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 60900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800505d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 60910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60950 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050580, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 60950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002640, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 60960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 60970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 60970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050580, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 60970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 60970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 60980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h5 + 60980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 60990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 60990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h7 + 61000 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800025c0, toState: E, child: , data: tagged Invalid , id: 'h0 } + 61010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61010 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 61010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 61020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 61040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1829 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6104 + 61050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1830 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6105 + 61060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1831 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6106 + 61070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1832 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6107 +instret:1833 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6107 + 61080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1834 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6108 +instret:1835 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6108 + 61090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050588, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1836 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6109 +instret:1837 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6109 + 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1838 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6110 +instret:1839 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6110 + 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050590, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 61120 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050600, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 61120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1840 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6112 + 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050598, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002650, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1841 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6113 + 61140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002650, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 61140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1842 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6114 + 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02600, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61150 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1843 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6115 +instret:1844 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6115 + 61160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02608, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1845 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6116 +instret:1846 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6116 + 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02610, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1847 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6117 +instret:1848 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6117 + 61180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02618, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1849 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6118 +instret:1850 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6118 + 61190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002600, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h0 + 61190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h3 + 61200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02620, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02628, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02630, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02638, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61310 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800505c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800505c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 + 61340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61350 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002600, toState: E, child: , data: tagged Invalid , id: 'h0 } + 61350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h1 + 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 61370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 61370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 61390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002600, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1851 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6139 + 61400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002608, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1852 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6140 + 61410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002610, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1853 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6141 + 61420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002618, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1854 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6142 +instret:1855 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6142 + 61430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002620, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:1856 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6143 +instret:1857 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6143 + 61440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002628, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050608, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1858 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6144 +instret:1859 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6144 + 61450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050608, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002630, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800505d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1860 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6145 +instret:1861 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6145 + 61460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800505d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800505d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050610, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 61470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050610, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 61470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800505d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1862 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6147 + 61480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800505d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800505d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002638, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050618, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1863 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6148 + 61490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050618, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 61490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:1864 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6149 + 61500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02640, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1865 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6150 +instret:1866 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6150 + 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02648, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1867 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6151 +instret:1868 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6151 + 61520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02650, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1869 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6152 +instret:1870 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6152 + 61530 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002680, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 61530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02658, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1871 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6153 +instret:1872 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6153 + 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 61540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 61550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800505f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 61600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61620 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002640, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02660, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02668, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02678, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 61660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 61670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002640, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1873 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6167 + 61680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 61680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002648, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:1874 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6168 + 61690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 61690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002650, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:1875 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6169 + 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 61700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002658, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:1876 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6170 +instret:1877 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6170 + 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 61710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002660, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002690, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1878 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6171 +instret:1879 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6171 + 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002690, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002668, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61720 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1880 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6172 +instret:1881 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6172 + 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 61730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1882 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6173 +instret:1883 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6173 + 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 61740 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050650, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050650, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 61750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1884 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6175 + 61760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050648, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 61760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050658, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 61760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1885 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6176 + 61770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 61770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800026c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1886 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6177 + 61780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800026c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 61780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800026d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1887 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6178 +instret:1888 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6178 + 61790 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800026c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 61790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800026d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 61790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800026d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1889 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6179 + 61800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800026d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 61930 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050600, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 61950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 61950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050600, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 61950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 61970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 61970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 61980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 61980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 61980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 61990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 61990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050610, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 61990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002670, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 61990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050688, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 62000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050680, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 62000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050688, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 62000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050618, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002678, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050690, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1890 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6201 + 62020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050690, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 62020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050620, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1891 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6203 +instret:1892 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6203 + 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050698, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02688, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1893 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6204 +instret:1894 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6204 + 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02698, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 62070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 + 62240 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002680, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 62250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 62250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 62260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 62290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002680, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1895 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6229 + 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050628, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002688, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1896 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6230 + 62310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002690, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1897 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6231 + 62320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050630, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 62320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002708, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1898 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6232 +instret:1899 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6232 + 62330 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002700, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 62330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002708, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 62330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1900 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6233 +instret:1901 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6233 + 62340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050638, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002698, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002710, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 62350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002710, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 62350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002718, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1902 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6236 +instret:1903 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6236 + 62370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002718, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1904 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6237 +instret:1905 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6237 + 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 62400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1906 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6241 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1907 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6242 +instret:1908 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6243 +instret:1909 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6244 +instret:1910 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6244 +instret:1911 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6245 + 62550 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050648, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050648, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050640, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 62580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050648, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 62590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 62600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050650, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800506c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 62620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800506c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800506c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 62620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050658, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800506d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1912 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6263 + 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800506d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 62640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050660, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800506d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1913 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6265 +instret:1914 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6265 + 62660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800506d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1915 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6266 +instret:1916 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6266 + 62670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 + 62690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h5 + 62860 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800026c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 62870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 62870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 62880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 62880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 62880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 62890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 62900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 62910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1917 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6291 + 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 62920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1918 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6292 + 62930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1919 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6293 + 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 62940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 62940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002748, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1920 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6294 +instret:1921 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6294 + 62950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002740, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 62950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002748, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 62950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1922 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6295 +instret:1923 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6295 + 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 62960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 62960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002750, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 62970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002750, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 62970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 62980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002758, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1924 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6298 +instret:1925 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6298 + 62990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 62990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002758, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 62990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 62990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1926 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6299 +instret:1927 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6299 + 63000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1928 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6303 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1929 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6304 +instret:1930 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6305 +instret:1931 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6306 +instret:1932 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6306 +instret:1933 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6307 + 63170 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050680, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 63180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63180 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 63180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 63190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 63220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 63220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050708, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 63240 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050700, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050708, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 63240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050710, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1934 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6325 + 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050710, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 63260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800506a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800506a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800506a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050718, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1935 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6327 +instret:1936 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6327 + 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050718, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02708, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1937 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6328 +instret:1938 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6328 + 63290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02718, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 63310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h1 + 63480 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002700, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 63500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 63500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 63520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 63530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002700, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1939 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6353 + 63540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002708, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1940 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6354 + 63550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002710, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1941 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6355 + 63560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002788, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1942 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6356 +instret:1943 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6356 + 63570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002780, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002788, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 63570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1944 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6357 +instret:1945 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6357 + 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002718, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002790, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002790, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 63590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002798, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1946 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6360 +instret:1947 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6360 + 63610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002798, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02728, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1948 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6361 +instret:1949 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6361 + 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02738, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002720, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1950 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6365 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002728, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1951 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6366 +instret:1952 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6367 +instret:1953 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6368 +instret:1954 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6368 +instret:1955 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6369 + 63790 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800506c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 63800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63800 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 63800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 63830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 63830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 63840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 63840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 63850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002730, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050748, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 63860 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050740, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 63860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050748, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 63860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800506d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 63870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002738, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 63870 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050750, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1956 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6387 + 63880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050750, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 63880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 63890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800506e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 63890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050758, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1957 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6389 +instret:1958 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6389 + 63900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050758, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 63900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02748, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1959 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6390 +instret:1960 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6390 + 63910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 63910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 63920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02758, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 63920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 63930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 + 63930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 63940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 63940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 64100 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002740, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 64120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 64120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800506e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 64140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 64150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002740, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1961 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6415 + 64160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800506e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800506e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002748, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1962 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6416 + 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002750, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1963 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6417 + 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800027c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1964 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6418 +instret:1965 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6418 + 64190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800027c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800027c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 64190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800506f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1966 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6419 +instret:1967 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6419 + 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800506f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800506f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002758, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64200 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800027d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800027d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 64210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800027d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1968 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6422 +instret:1969 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6422 + 64230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800027d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02768, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1970 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6423 +instret:1971 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6423 + 64240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02778, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002760, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1972 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6427 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002768, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1973 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6428 +instret:1974 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6429 +instret:1975 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6430 +instret:1976 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6430 +instret:1977 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6431 + 64410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050700, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 64420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 64420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 64460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 64460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002770, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64470 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050788, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 64480 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050780, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 64480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050788, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 64480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002778, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050790, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1978 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6449 + 64500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050790, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 64500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050798, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1979 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6451 +instret:1980 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6451 + 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050798, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02788, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1981 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6452 +instret:1982 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6452 + 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02798, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 64550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 + 64720 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002780, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 64740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 64740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 64760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002780, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1983 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6477 + 64780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 64780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002788, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1984 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6478 + 64790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002790, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:1985 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6479 + 64800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 64800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64800 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002808, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1986 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6480 +instret:1987 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6480 + 64810 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002800, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 64810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002808, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 64810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:1988 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6481 +instret:1989 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6481 + 64820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 64820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002798, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 64820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 64830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 64830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 64840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002818, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:1990 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6484 +instret:1991 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6484 + 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002818, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 64850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:1992 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6485 +instret:1993 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6485 + 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 64860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 64870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 64870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 64880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 64880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 64890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 64890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 64890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1994 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6489 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:1995 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6490 +instret:1996 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6491 +instret:1997 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6492 +instret:1998 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6492 +instret:1999 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6493 + 65030 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050740, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 65080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 65080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800507c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 65100 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800507c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 65100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800507c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 65100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800507d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2000 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6511 + 65120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800507d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 65120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800507d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2001 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6513 +instret:2002 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6513 + 65140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800507d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2003 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6514 +instret:2004 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6514 + 65150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 + 65170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h5 + 65340 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800027c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 65350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65350 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 65350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 65360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2005 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6539 + 65400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2006 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6540 + 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2007 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6541 + 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002848, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2008 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6542 +instret:2009 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6542 + 65430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002840, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002848, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 65430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2010 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6543 +instret:2011 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6543 + 65440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 65450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002858, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2012 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6546 +instret:2013 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6546 + 65470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002858, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2014 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6547 +instret:2015 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6547 + 65480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2016 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6551 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2017 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6552 +instret:2018 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6553 +instret:2019 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6554 +instret:2020 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6554 +instret:2021 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6555 + 65650 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050780, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 65660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65660 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 65660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 65670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 65690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 65700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 65710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050808, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 65720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050800, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050808, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 65720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 65730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 65730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2022 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6573 + 65740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 65740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800507a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800507a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800507a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 65750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02800, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050818, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2023 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6575 +instret:2024 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6575 + 65760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050818, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02808, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2025 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6576 +instret:2026 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6576 + 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02810, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02818, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 65780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 65790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 65790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 65800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h1 + 65960 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002800, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 65970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65970 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 65970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 65970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 65980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 65980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 65980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 65990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 65990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 65990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 65990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 66000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 66010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002800, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2027 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6601 + 66020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002808, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2028 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6602 + 66030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002810, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2029 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6603 + 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002888, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2030 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6604 +instret:2031 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6604 + 66050 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002880, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002888, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 66050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2032 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6605 +instret:2033 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6605 + 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002818, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002890, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002890, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 66070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02820, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002898, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2034 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6608 +instret:2035 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6608 + 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002898, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02828, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2036 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6609 +instret:2037 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6609 + 66100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02830, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02838, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002820, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2038 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6613 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002828, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2039 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6614 +instret:2040 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6615 +instret:2041 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6616 +instret:2042 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6616 +instret:2043 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6617 + 66270 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800507c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 66290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 66320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002830, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66330 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050848, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66340 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050840, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 66340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050848, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 66340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800507d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002838, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2044 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6635 + 66360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 66360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800507e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02840, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050858, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2045 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6637 +instret:2046 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6637 + 66380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050858, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02848, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2047 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6638 +instret:2048 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6638 + 66390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02850, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02858, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 + 66410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 66580 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002840, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 66590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66590 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 66590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 66600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 66600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 66620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 66630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002840, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2049 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6663 + 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002848, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2050 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6664 + 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002850, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2051 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6665 + 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800507f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800028c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2052 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6666 +instret:2053 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6666 + 66670 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800028c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800028c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 66670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800507f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2054 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6667 +instret:2055 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6667 + 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800507f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800507f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002858, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800028d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800028d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 66690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02860, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800028d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2056 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6670 +instret:2057 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6670 + 66710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800028d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02868, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2058 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6671 +instret:2059 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6671 + 66720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 66720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02870, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 66730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02878, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800028c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 66740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 66740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 66750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002860, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2060 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6675 + 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 66760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002868, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2061 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6676 +instret:2062 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6677 +instret:2063 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6679 +instret:2064 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6679 +instret:2065 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6680 + 66890 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050800, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050800, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050808, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 66930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 66930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 66940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050810, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 66950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002870, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050888, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 66960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050880, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 66960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050888, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 66960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050818, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 66970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002878, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 66970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050890, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2066 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6697 + 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050890, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 66980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 66980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050820, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 66990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02880, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 66990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050898, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2067 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6699 +instret:2068 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6699 + 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050898, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02888, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2069 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6700 +instret:2070 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6700 + 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02890, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02898, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 67030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h3 + 67040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050828, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050830, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050838, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67200 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002880, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 67210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 67220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 67250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002880, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2071 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6725 + 67260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002888, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2072 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6726 + 67270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002890, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2073 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6727 + 67280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002898, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2074 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6728 +instret:2075 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6728 + 67290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2076 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6729 +instret:2077 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6729 + 67300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002908, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2078 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6730 +instret:2079 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6730 + 67310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002908, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 67310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002910, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2080 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6731 +instret:2081 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6731 + 67320 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002900, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002910, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 67320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002918, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002918, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:2082 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6733 +instret:2083 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6734 +instret:2084 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6735 +instret:2085 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6736 +instret:2086 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6736 +instret:2087 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6737 + 67390 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002900, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 67400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67400 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67510 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050840, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 67530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050840, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 67560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050850, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67570 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800508c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 67580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800508c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800508c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 67580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050858, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800508d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2088 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 6759 + 67600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800508d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 67600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050860, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800508d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2089 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6761 +instret:2090 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6761 + 67620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800508d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2091 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6762 +instret:2092 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6762 + 67630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67650 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800028c0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 67650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h5 + 67650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 67660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050868, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 67680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050870, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67700 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002940, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 67700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050878, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002940, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 67780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h1 + 67810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800028c0, toState: E, child: , data: tagged Invalid , id: 'h0 } + 67820 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050880, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 67820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2093 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6785 + 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 67860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2094 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6786 + 67870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 67870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2095 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6787 + 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050880, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2096 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6788 +instret:2097 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6788 + 67890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 67890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2098 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6789 +instret:2099 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6789 + 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 67900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2100 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6790 +instret:2101 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6790 + 67910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 67910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2102 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6791 +instret:2103 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6791 + 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050888, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 67920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002948, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 67930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002948, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002948, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2104 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6793 + 67940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050890, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 67940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002950, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2105 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6794 + 67950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002950, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002950, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2106 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6795 + 67960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050898, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 67960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 67960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002958, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2107 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6796 +instret:2108 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6796 + 67970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002958, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002958, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 67970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2109 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6797 +instret:2110 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6797 + 67980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 67980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 67980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02900, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2111 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6798 +instret:2112 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6798 + 67990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 67990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 67990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02908, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 67990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2113 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6799 +instret:2114 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6799 + 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02910, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68010 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050900, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02918, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68020 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002900, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 68020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 68030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050908, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050908, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 68050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050910, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050910, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 68070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050918, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050918, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 68090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02920, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02928, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02930, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68130 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800508c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 68130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002980, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02938, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68140 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 68150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800508c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 + 68160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 68180 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002900, toState: E, child: , data: tagged Invalid , id: 'h0 } + 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 68200 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002980, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 68210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002900, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2115 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6822 + 68230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002908, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2116 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6823 + 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002910, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2117 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6824 + 68250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68250 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002918, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2118 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6825 +instret:2119 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6825 + 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002920, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2120 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6826 +instret:2121 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6826 + 68270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002928, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800508c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2122 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6827 +instret:2123 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6827 + 68280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800508c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800508c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2124 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6828 +instret:2125 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6828 + 68290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002930, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800508d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800508d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800508d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002988, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2126 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6830 + 68310 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050940, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 68310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002988, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002988, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2127 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6831 + 68320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002938, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002990, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2128 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6832 + 68330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002990, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002990, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2129 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6833 +instret:2130 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6833 + 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02940, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002998, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2131 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6834 +instret:2132 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6834 + 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002998, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002998, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02948, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2133 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6835 +instret:2134 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6835 + 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02950, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2135 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6836 +instret:2136 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6836 + 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02958, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68380 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002940, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 68380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 68380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 68390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050948, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050948, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 68410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050950, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050950, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 68430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800508f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050958, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050958, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 68450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02960, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02968, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02970, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050900, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 68490 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800029c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02978, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050900, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h3 + 68520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 68540 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002940, toState: E, child: , data: tagged Invalid , id: 'h0 } + 68550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 68560 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800029c0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002940, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2137 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6858 + 68590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002948, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2138 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6859 + 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002950, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2139 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6860 + 68610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68610 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002958, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2140 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6861 +instret:2141 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6861 + 68620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002960, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2142 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6862 +instret:2143 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6862 + 68630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002968, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2144 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6863 +instret:2145 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6863 + 68640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2146 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6864 +instret:2147 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6864 + 68650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002970, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050910, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050910, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050910, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800029c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2148 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6866 + 68670 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050980, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 68670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800029c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800029c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050918, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2149 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6867 + 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050918, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050918, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002978, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800029d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2150 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6868 + 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800029d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800029d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050920, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2151 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6869 +instret:2152 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6869 + 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050920, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050920, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02980, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800029d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2153 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6870 +instret:2154 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6870 + 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800029d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800029d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02988, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2155 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6871 +instret:2156 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6871 + 68720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02990, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2157 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6872 +instret:2158 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6872 + 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02998, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68740 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002980, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 68740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h7 + 68740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 + 68750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050928, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050928, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050928, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050988, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050988, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 68770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050930, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050930, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050930, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 68780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050990, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050990, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 68790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050938, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68800 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050940, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 68800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050938, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050938, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 68800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68810 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 68810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050940, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050940, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050940, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 68820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050998, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 68830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050998, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 68830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 68850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 + 68900 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002980, toState: E, child: , data: tagged Invalid , id: 'h0 } + 68910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68910 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 68910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 68920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 68940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002980, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2159 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6894 + 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 68950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002988, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2160 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6895 + 68960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 68960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002990, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2161 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6896 + 68970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 68970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 68970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002998, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2162 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6897 +instret:2163 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6897 + 68980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 68980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050948, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2164 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6898 +instret:2165 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6898 + 68990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 68990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050948, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 68990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050948, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 68990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 68990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2166 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6899 +instret:2167 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6899 + 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050950, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2168 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6900 +instret:2169 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6900 + 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050950, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050950, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69020 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002a00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 69020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050958, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2170 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6902 + 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050958, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050958, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002a08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2171 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6903 + 69040 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800509c0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002a08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 69040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050960, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2172 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6904 + 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050960, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050960, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69050 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2173 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6905 +instret:2174 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6905 + 69060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2175 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6906 +instret:2176 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6906 + 69070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2177 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6907 +instret:2178 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6907 + 69080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2179 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6908 +instret:2180 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6908 + 69090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002a00, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 69090 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h15, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800029c0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 69100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 69110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002a18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050970, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050970, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050970, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69150 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050980, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050978, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050978, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050978, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050980, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050980, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050980, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 + 69250 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800029c0, toState: E, child: , data: tagged Invalid , id: 'h0 } + 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 69270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 69290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2181 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6929 + 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2182 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6930 + 69310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2183 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6931 + 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2184 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6932 +instret:2185 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6932 + 69330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050988, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2186 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6933 +instret:2187 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6933 + 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050988, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050988, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800509d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2188 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6934 +instret:2189 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6934 + 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800509d8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050990, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2190 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6935 +instret:2191 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6935 + 69360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050990, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050990, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 69370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050998, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2192 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6937 + 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050998, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050998, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2193 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6938 + 69390 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002a40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 69390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2194 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6939 + 69400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002a48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2195 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6940 +instret:2196 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6940 + 69410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050a00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 69410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002a48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2197 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6941 +instret:2198 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6941 + 69420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2199 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6942 +instret:2200 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6942 + 69430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2201 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6943 +instret:2202 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6943 + 69440 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002a00, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 69440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h0 + 69450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69460 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002a40, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002a58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69520 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800509c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69530 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 + 69560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h2 + 69600 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002a00, toState: E, child: , data: tagged Invalid , id: 'h0 } + 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 69620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2203 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6964 + 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2204 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6965 + 69660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2205 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6966 + 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2206 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6967 +instret:2207 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6967 + 69680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2208 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6968 +instret:2209 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6968 + 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050a08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2210 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6969 +instret:2211 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6969 + 69700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050a08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2212 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6970 +instret:2213 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6970 + 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800509d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050a10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050a10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 69720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800509d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2214 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6972 + 69730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800509d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800509d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 69730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2215 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 6973 + 69740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 69740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800509e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2216 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 6974 + 69750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800509e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800509e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2217 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 6975 +instret:2218 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 6975 + 69760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2219 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 6976 +instret:2220 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 6976 + 69770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2221 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 6977 +instret:2222 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 6977 + 69780 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002a80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2223 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 6978 +instret:2224 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 6978 + 69790 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002a40, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 + 69790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h7 + 69800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 69810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69810 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 69820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 69830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050a40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 69840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800509f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 69850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69890 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050a00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 69900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 69910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 69910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 69910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h2 + 69920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 69950 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002a40, toState: E, child: , data: tagged Invalid , id: 'h0 } + 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 69960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 69970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 69970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 69980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 69990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2225 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 6999 + 70000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2226 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7000 + 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2227 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7001 + 70020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2228 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7002 +instret:2229 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7002 + 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2230 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7003 +instret:2231 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7003 + 70040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2232 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7004 +instret:2233 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7004 + 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2234 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7005 +instret:2235 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7005 + 70060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 70070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2236 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7007 + 70080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050a58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2237 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7008 + 70090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050a58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 70090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2238 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7009 + 70100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2239 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7010 +instret:2240 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7010 + 70110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2241 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7011 +instret:2242 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7011 + 70120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2243 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7012 +instret:2244 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7012 + 70130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002ac0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2245 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7013 +instret:2246 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7013 + 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 + 70140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 + 70150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70200 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002ac0, toState: S, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 70210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02aa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02aa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ab0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70250 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050a80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ab8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70260 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002a80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 70270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 70270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 70280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 70280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2247 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7031 + 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2248 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7032 + 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2249 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7033 + 70340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2250 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7034 +instret:2251 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7034 + 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002aa0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2252 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7035 +instret:2253 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7035 + 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002aa8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2254 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7036 +instret:2255 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7036 + 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002ad8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2256 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7037 +instret:2257 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7037 + 70380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050a88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 70380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 70390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050a98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2258 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7039 + 70400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050a98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 70400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2259 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7040 + 70410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 70410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002b08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2260 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7041 + 70420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002b08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 70420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2261 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7042 +instret:2262 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7042 + 70430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002b00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 70430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 70430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002b18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2263 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7043 + 70440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002b18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 70570 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050a40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 70580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70580 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 70580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 70590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 70620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ab0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70640 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050ac0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 70640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050a58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050a58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050a58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ab8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050ad0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2264 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7065 + 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050ad0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 70660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ac0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050ad8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2265 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7067 +instret:2266 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7067 + 70680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050ad8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ac8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2267 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7068 +instret:2268 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7068 + 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ad0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ad8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70710 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002ac0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h5 + 70710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 70720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 70750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 70770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ae0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ae8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02af0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02af8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 70870 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002ac0, toState: E, child: , data: tagged Invalid , id: 'h0 } + 70880 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050a80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 70890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 70910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ac0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2269 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7091 + 70920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 70920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ac8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2270 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7092 + 70930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 70930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050a80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 70930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ad0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2271 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7093 + 70940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 70940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ad8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2272 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7094 +instret:2273 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7094 + 70950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 70950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2274 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7095 +instret:2275 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7095 + 70960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 70960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 70960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2276 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7096 +instret:2277 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7096 + 70970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 70970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ae0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } +instret:2278 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7097 +instret:2279 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7097 + 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 70980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ae8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 70990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002af0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 70990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2280 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7099 + 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050a90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2281 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7100 + 71010 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002b40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 71010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2282 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7101 + 71020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050a98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002af8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2283 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7102 +instret:2284 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7102 + 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 71030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050aa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } +instret:2285 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7103 +instret:2286 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7103 + 71040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050aa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050aa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002b58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2287 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7104 +instret:2288 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7104 + 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002b58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2289 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7105 +instret:2290 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7105 + 71060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 + 71080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 + 71090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050aa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050aa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050aa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ab8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ac0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ac0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71190 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002b00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 71210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 71230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2291 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7124 + 71250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2292 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7125 + 71260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2293 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7126 + 71270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2294 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7127 +instret:2295 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7127 + 71280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2296 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7128 +instret:2297 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7128 + 71290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050b08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2298 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7129 +instret:2299 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7129 + 71300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050b08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 71300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2300 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7130 +instret:2301 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7130 + 71310 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 71310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 71310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 71320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 71320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2302 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7132 + 71330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 71330 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2303 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7133 + 71340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002b88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 71340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2304 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7134 + 71350 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002b80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 71350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 71350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002b98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2305 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7135 +instret:2306 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7135 + 71360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002b98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:2307 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7136 + 71500 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050ac0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ac0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ac0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ac8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ac8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ac8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 71550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 71550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ad0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ad0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ad0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 71570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 71570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 71570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ad8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ad8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ad8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050b50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2308 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7158 + 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050b50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 71590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ae0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ae0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ae0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2309 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7160 +instret:2310 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7160 + 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2311 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7161 +instret:2312 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7161 + 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 71640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 71810 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002b40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 71830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 71830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 71860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 71860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2313 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7186 + 71870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 71870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71870 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2314 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7187 + 71880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050af0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2315 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7188 + 71890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050af0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050af0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 71890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2316 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7189 +instret:2317 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7189 + 71900 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002bc0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 71900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 71900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050af8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2318 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7190 +instret:2319 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7190 + 71910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050af8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050af8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 71910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 71910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002bd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002bd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 71920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 71930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002bd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2320 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7193 +instret:2321 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7193 + 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002bd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 71940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2322 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7194 +instret:2323 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7194 + 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 71950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 71960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 71960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 71970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 71970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 71980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 71980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 71980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2324 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7198 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2325 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7199 +instret:2326 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7200 +instret:2327 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7201 +instret:2328 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7201 +instret:2329 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7202 + 72120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 72130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 72130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 72170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 72170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 72190 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 72190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 72190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050b18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72200 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2330 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7220 + 72210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 72210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2331 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7222 +instret:2332 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7222 + 72230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2333 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7223 +instret:2334 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7223 + 72240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 72260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 72430 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002b80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 72450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 72470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2335 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7248 + 72490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2336 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7249 + 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2337 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7250 + 72510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002c08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2338 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7251 +instret:2339 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7251 + 72520 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002c00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002c08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 72520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2340 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7252 +instret:2341 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7252 + 72530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 72540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 72540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ba0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002c18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2342 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7255 +instret:2343 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7255 + 72560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002c18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ba8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2344 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7256 +instret:2345 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7256 + 72570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ba0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2346 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7260 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ba8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2347 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7261 +instret:2348 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7262 +instret:2349 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7263 +instret:2350 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7263 +instret:2351 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7264 + 72740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 72750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 72750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 72760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 72760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 72780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 72780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 72790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 72800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bb0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72800 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 72810 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050bc0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 72810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 72810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050b58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 72820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bb8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 72820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2352 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7282 + 72830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 72830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050b60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 72840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2353 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7284 +instret:2354 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7284 + 72850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 72850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2355 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7285 +instret:2356 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7285 + 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 72860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 72870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 72870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 72880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 + 72880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 72890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 72890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 73050 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002bc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 73060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73060 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 73060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 73070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 73070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 73090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 73100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bc0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2357 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7310 + 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bc8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2358 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7311 + 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bd0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2359 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7312 + 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002c48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2360 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7313 +instret:2361 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7313 + 73140 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002c40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002c48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 73140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2362 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7314 +instret:2363 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7314 + 73150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bd8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73150 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002c50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002c50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 73160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02be0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002c58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2364 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7317 +instret:2365 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7317 + 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002c58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02be8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2366 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7318 +instret:2367 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7318 + 73190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002be0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2368 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7322 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002be8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2369 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7323 +instret:2370 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7324 +instret:2371 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7325 +instret:2372 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7325 +instret:2373 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7326 + 73360 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 73380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050b88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 73410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 73410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050b90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bf0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 73430 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 73430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 73430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050b98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bf8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050c10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2374 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7344 + 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050c10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 73450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ba0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ba0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ba0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2375 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7346 +instret:2376 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7346 + 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2377 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7347 +instret:2378 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7347 + 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 73500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 73670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002c00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 73680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 73680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 73690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 73720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 73720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2379 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7372 + 73730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 73730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2380 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7373 + 73740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2381 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7374 + 73750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 73750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2382 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7375 +instret:2383 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7375 + 73760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002c80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 73760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 73760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2384 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7376 +instret:2385 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7376 + 73770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 73770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 73770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 73780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 73780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 73790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2386 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7379 +instret:2387 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7379 + 73800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2388 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7380 +instret:2389 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7380 + 73810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 73810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 73820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 73820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 73830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 73830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 73840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 73840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2390 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7384 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2391 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7385 +instret:2392 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7386 +instret:2393 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7387 +instret:2394 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7387 +instret:2395 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7388 + 73980 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050bc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 73990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 74000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 74030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 74030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050bd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 74050 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 74050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050bd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050c50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2396 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7406 + 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050c50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 74070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050be0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050be0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050be0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2397 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7408 +instret:2398 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7408 + 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2399 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7409 +instret:2400 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7409 + 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 74120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 74290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002c40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 74300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 74300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 74310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050be8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 74330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 74340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2401 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7434 + 74350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050be8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050be8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2402 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7435 + 74360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2403 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7436 + 74370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050bf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2404 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7437 +instret:2405 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7437 + 74380 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002cc0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 74380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 74380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050bf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2406 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7438 +instret:2407 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7438 + 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050bf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050bf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74390 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002cd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002cd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 74400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002cd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2408 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7441 +instret:2409 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7441 + 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002cd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2410 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7442 +instret:2411 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7442 + 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2412 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7446 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2413 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7447 +instret:2414 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7448 +instret:2415 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7449 +instret:2416 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7449 +instret:2417 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7450 + 74600 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 74620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 74650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 74670 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 74670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 74670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050c18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 74680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2418 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7468 + 74690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 74690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050c20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 74700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2419 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7470 +instret:2420 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7470 + 74710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050c98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2421 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7471 +instret:2422 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7471 + 74720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 74730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 74740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 74910 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002c80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 74930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 74930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 74940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 74950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 74960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 74960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 74960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2423 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7496 + 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 74970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2424 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7497 + 74980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 74980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 74980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2425 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7498 + 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 74990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 74990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2426 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7499 +instret:2427 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7499 + 75000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002d00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 75000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 75000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2428 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7500 +instret:2429 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7500 + 75010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 75020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ca0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002d18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2430 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7503 +instret:2431 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7503 + 75040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002d18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ca8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2432 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7504 +instret:2433 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7504 + 75050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ca0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2434 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7508 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ca8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2435 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7509 +instret:2436 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7510 +instret:2437 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7511 +instret:2438 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7511 +instret:2439 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7512 + 75220 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 75230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75230 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 75230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 75270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cb0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050cc0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 75290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cb8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050cd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2440 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7530 + 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050cd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 75310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050c60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2441 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7532 +instret:2442 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7532 + 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2443 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7533 +instret:2444 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7533 + 75340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 + 75360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 75530 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002cc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 75540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 75540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 75550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 75550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 75570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cc0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2445 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7558 + 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cc8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2446 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7559 + 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cd0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2447 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7560 + 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2448 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7561 +instret:2449 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7561 + 75620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002d40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 75620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 75620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2450 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7562 +instret:2451 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7562 + 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cd8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 75640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ce0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002d58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2452 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7565 +instret:2453 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7565 + 75660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002d58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ce8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2454 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7566 +instret:2455 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7566 + 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ce0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2456 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7570 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ce8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2457 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7571 +instret:2458 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7572 +instret:2459 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7573 +instret:2460 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7573 +instret:2461 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7574 + 75840 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 75850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75850 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 75850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 75860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 75860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 75880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 75880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 75890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050c90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 75900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cf0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 75910 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 75910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 75910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050c98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 75920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cf8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 75920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2462 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7592 + 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 75930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ca0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 75940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2463 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7594 +instret:2464 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7594 + 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 75950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2465 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7595 +instret:2466 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7595 + 75960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 75960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 75970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 75970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 75980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 75980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 75990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 76150 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002d00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 76170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 76190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 76200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2467 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7620 + 76210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ca8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2468 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7621 + 76220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2469 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7622 + 76230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2470 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7623 +instret:2471 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7623 + 76240 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002d80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 76240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 76240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2472 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7624 +instret:2473 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7624 + 76250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 76260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 76260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2474 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7627 +instret:2475 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7627 + 76280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2476 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7628 +instret:2477 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7628 + 76290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2478 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7632 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2479 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7633 +instret:2480 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7634 +instret:2481 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7635 +instret:2482 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7635 +instret:2483 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7636 + 76460 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050cc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 76480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 76510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 76510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050cd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 76530 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 76530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 76530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050cd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2484 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7654 + 76550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 76550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ce0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2485 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7656 +instret:2486 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7656 + 76570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2487 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7657 +instret:2488 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7657 + 76580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 76600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 76770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002d40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 76780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 76780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 76790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 76790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 76810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 76820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 76820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2489 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7682 + 76830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ce8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 76830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2490 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7683 + 76840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2491 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7684 + 76850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050cf0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 76850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2492 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7685 +instret:2493 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7685 + 76860 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002dc0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 76860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 76860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050cf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2494 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7686 +instret:2495 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7686 + 76870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050cf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050cf8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 76870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 76870 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 76880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 76880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 76890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002dd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2496 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7689 +instret:2497 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7689 + 76900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002dd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 76900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2498 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7690 +instret:2499 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7690 + 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 76910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 76920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 76920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 76930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 76930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 76940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 76940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 76940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2500 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7694 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2501 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7695 +instret:2502 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7696 +instret:2503 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7697 +instret:2504 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7697 +instret:2505 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7698 + 77080 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 77090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77090 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 77090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 77100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 77130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 77150 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 77150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050d18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2506 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7716 + 77170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050d90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 77170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050d20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2507 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7718 +instret:2508 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7718 + 77190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050d98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2509 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7719 +instret:2510 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7719 + 77200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 77220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 77390 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002d80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 77400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77400 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 77400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 77410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h15, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 77410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 77430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2511 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7744 + 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2512 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7745 + 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2513 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7746 + 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77470 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2514 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7747 +instret:2515 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7747 + 77480 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002e00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 77480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2516 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7748 +instret:2517 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7748 + 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 77500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02da0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002e18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2518 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7751 +instret:2519 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7751 + 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002e18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02da8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2520 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7752 +instret:2521 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7752 + 77530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02db0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02db8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002da0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2522 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7756 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002da8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2523 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7757 +instret:2524 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7758 +instret:2525 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7759 +instret:2526 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7759 +instret:2527 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7760 + 77700 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 77710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77710 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 77710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 77720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 77720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 77740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 77740 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 77750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 77750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 77760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002db0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 77770 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050dc0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 77770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 77770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050d58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 77780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002db8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 77780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2528 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7778 + 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050dd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 77790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050d60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 77800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77800 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050dd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2529 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7780 +instret:2530 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7780 + 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050dd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 77810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2531 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7781 +instret:2532 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7781 + 77820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 77820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 77830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 77830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 77840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 + 77840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 77850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 78010 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002dc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 78030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 78030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 78050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 78060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dc0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2533 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7806 + 78070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dc8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2534 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7807 + 78080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dd0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2535 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7808 + 78090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2536 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7809 +instret:2537 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7809 + 78100 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002e40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 78100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 78100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2538 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7810 +instret:2539 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7810 + 78110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dd8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 78120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02de0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002e58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2540 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7813 +instret:2541 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7813 + 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002e58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02de8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2542 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7814 +instret:2543 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7814 + 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02df0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02df8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002de0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2544 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7818 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002de8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2545 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7819 +instret:2546 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7820 +instret:2547 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7821 +instret:2548 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7821 +instret:2549 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7822 + 78320 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 78330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 78330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78360 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 78370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 78370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050d90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002df0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 78390 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 78390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 78390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002df8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78400 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2550 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7840 + 78410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 78410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050da0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2551 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7842 +instret:2552 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7842 + 78430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2553 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7843 +instret:2554 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7843 + 78440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 78460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 78630 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002e00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 78640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 78640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 78650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 78650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 78670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 78680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2555 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7868 + 78690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050da8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2556 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7869 + 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2557 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7870 + 78710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050db0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 78710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78710 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2558 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7871 +instret:2559 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7871 + 78720 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002e80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 78720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 78720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050db8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2560 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7872 +instret:2561 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7872 + 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050db8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050db8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 78730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 78730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 78740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 78740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2562 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7875 +instret:2563 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7875 + 78760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2564 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7876 +instret:2565 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7876 + 78770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 78770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 78780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 78780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 78790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 78800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2566 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7880 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2567 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7881 +instret:2568 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7882 +instret:2569 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7883 +instret:2570 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7883 +instret:2571 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7884 + 78940 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050dc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 78950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78950 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 78950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 78960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 78960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 78960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 78980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050dc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 78980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 78980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 78990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 78990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 78990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 78990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050dd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 79010 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 79010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 79010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050dd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2572 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7902 + 79030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050e50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 79030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050de0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2573 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7904 +instret:2574 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7904 + 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2575 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7905 +instret:2576 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7905 + 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 79080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 79250 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002e40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 79270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2577 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7930 + 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2578 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7931 + 79320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2579 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7932 + 79330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050df0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 79330 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2580 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7933 +instret:2581 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7933 + 79340 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002ec0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 79340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 79340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050df8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2582 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7934 +instret:2583 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7934 + 79350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050df8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050df8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79350 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002ed0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 79360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002ed0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 79360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002ed8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2584 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7937 +instret:2585 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7937 + 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002ed8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2586 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7938 +instret:2587 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7938 + 79390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 79410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2588 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7942 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2589 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7943 +instret:2590 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7944 +instret:2591 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7945 +instret:2592 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7945 +instret:2593 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7946 + 79560 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 79570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79570 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 79570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 79580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 79590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 79600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 79610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 79630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 79630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050e18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2594 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 7964 + 79650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 79650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2595 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7966 +instret:2596 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7966 + 79670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2597 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 7967 +instret:2598 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 7967 + 79680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 79700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 79870 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002e80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 79880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 79880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 79890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 79890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 79890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 79900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 79910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 79910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 79920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 79920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 79920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2599 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 7992 + 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 79930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2600 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 7993 + 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2601 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 7994 + 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 79950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 79950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002f08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2602 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 7995 +instret:2603 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 7995 + 79960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002f00, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002f08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 79960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2604 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 7996 +instret:2605 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 7996 + 79970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 79970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 79970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 79970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 79980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 79980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 79990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 79990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ea0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 79990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002f18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2606 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 7999 +instret:2607 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 7999 + 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002f18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ea8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2608 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8000 +instret:2609 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8000 + 80010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02eb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02eb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ea0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2610 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8004 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ea8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2611 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8005 +instret:2612 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8006 +instret:2613 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8007 +instret:2614 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8007 +instret:2615 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8008 + 80180 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 80200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 80230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 80230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002eb0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 80250 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050ec0, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 80250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 80250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050e58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002eb8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2616 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8026 + 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 80270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050e60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ec0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2617 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8028 +instret:2618 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8028 + 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ec8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2619 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8029 +instret:2620 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8029 + 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ed0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ed8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 + 80320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h2 + 80490 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002ec0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 80500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 80500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 80510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 80540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ec0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2621 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8054 + 80550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ec8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80550 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2622 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8055 + 80560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ed0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2623 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8056 + 80570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80570 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002f48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2624 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8057 +instret:2625 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8057 + 80580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002f40, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 80580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002f48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 80580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2626 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8058 +instret:2627 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 8058 + 80590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ed8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002f50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 80600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002f50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 80600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ee0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002f58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2628 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8061 +instret:2629 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8061 + 80620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002f58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ee8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2630 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8062 +instret:2631 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8062 + 80630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ef0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ef8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ee0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2632 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8066 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ee8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2633 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8067 +instret:2634 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8068 +instret:2635 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8069 +instret:2636 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8069 +instret:2637 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8070 + 80800 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 80810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80810 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 80810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 80820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 80820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050e88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 80840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 80840 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 80850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 80850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050e90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 80860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ef0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 80870 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050f00, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f08, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 80870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050e98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 80880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ef8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 80880 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050f10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2638 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8088 + 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050f10, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 80890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050ea0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 80900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80900 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2639 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8090 +instret:2640 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8090 + 80910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f18, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 80910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2641 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8091 +instret:2642 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8091 + 80920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 80920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 80930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 80930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 80940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 80940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 80950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 80950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 81110 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002f00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 81120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81120 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 81120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 81130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 81160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f00, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2643 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8116 + 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f08, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2644 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8117 + 81180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f10, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050eb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2645 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8118 + 81190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050eb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050eb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81190 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2646 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8119 +instret:2647 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8119 + 81200 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002f80, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 81200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 81200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2648 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8120 +instret:2649 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 8120 + 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050eb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f18, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 81220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 81220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2650 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8123 +instret:2651 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8123 + 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2652 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8124 +instret:2653 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8124 + 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f20, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2654 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8128 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f28, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2655 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8129 +instret:2656 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8130 +instret:2657 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8131 +instret:2658 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8131 +instret:2659 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8132 + 81420 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050ec0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 81440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ec0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ec8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ec8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ec8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 81470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ed0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ed0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ed0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f30, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 81490 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050f40, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 81490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f48, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 81490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ed8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f38, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050f50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2660 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8150 + 81510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050f50, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 81510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050ee0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2661 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8152 +instret:2662 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8152 + 81530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f58, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2663 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8153 +instret:2664 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8153 + 81540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 81560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 81730 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002f40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 81750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 81750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ee8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 81780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 81780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f40, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2665 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8178 + 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ee8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050ee8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 81790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f48, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2666 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8179 + 81800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f50, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2667 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8180 + 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ef0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 81810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81810 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2668 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8181 +instret:2669 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8181 + 81820 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002fc0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 81820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 81820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2670 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8182 +instret:2671 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 8182 + 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ef8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 81830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f58, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 81830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002fd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 81840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002fd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 81840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 81850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002fd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2672 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8185 +instret:2673 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8185 + 81860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002fd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 81860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2674 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8186 +instret:2675 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8186 + 81870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 81870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 81880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 81880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 81890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 81890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 81900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 81900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 81900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f60, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2676 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8190 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f68, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2677 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8191 +instret:2678 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8192 +instret:2679 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8193 +instret:2680 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8193 +instret:2681 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8194 + 82040 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050f00, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 82050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82050 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 82050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 82060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f00, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82080 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 82090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f10, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f70, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 82110 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h1, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050f80, fromState: I, toState: S, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f88, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 82110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f18, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f78, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2682 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8212 + 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f90, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 82130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f20, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2683 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8214 +instret:2684 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8214 + 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f98, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2685 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8215 +instret:2686 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8215 + 82160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h3 + 82180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 82350 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002f80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 82360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82360 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 82360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 82370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 82370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 82390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 82400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f80, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2687 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8240 + 82410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050f28, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f88, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2688 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8241 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f90, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } +instret:2689 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8242 + 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f30, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2690 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8243 +instret:2691 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8243 + 82440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } +instret:2692 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8244 +instret:2693 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 8244 + 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f38, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f98, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2694 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8247 +instret:2695 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8247 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2696 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8248 +instret:2697 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8248 + 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fa0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2698 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8252 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fa8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2699 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8253 +instret:2700 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8254 +instret:2701 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8255 +instret:2702 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8255 +instret:2703 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8256 + 82660 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050f40, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 82670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82670 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 82670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 82680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050f40, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f48, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 82710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 82710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f50, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fb0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82720 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 82730 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h3, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050fc0, fromState: I, toState: S, canUpToE: True, id: 'h3, child: , isPrefetchRq: False } + 82730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 82730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050f58, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fb8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 82740 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050fd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2704 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8274 + 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050fd0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 82750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f60, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050fd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:2705 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8276 +instret:2706 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8276 + 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050fd8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } +instret:2707 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8277 +instret:2708 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8277 + 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 82790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 82800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h5 + 82800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 82810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h1 + 82810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 82820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f70, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 82840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f78, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 82860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 82870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 82880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fe0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fe8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ff0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ff8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 82970 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002fc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 82980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 82990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 82990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 82990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 82990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 82990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 83000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 83010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 83020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fc0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2709 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8302 + 83030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 83030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc18 } + 83030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fc8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 83030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } +instret:2710 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8303 + 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdc1c } + 83040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fd0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 83040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } +instret:2711 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8304 + 83050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 83050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe0 } + 83050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fd8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 83050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } +instret:2712 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8305 +instret:2713 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8305 + 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe4 } + 83060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fe0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2714 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8306 +instret:2715 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [1]] 8306 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fe8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2716 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8307 +instret:2717 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8307 +instret:2718 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8308 +instret:2719 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8308 +instret:2720 PC:0x1ffff000000000000ffffffffffe023f8 instr:0x0007bf03 iType:Ld [doCommitNormalInst [0]] 8310 +instret:2721 PC:0x1ffff000000000000ffffffffffe023fc instr:0x0087be83 iType:Ld [doCommitNormalInst [0]] 8311 +instret:2722 PC:0x1ffff000000000000ffffffffffe02400 instr:0x0107be03 iType:Ld [doCommitNormalInst [0]] 8312 +instret:2723 PC:0x1ffff000000000000ffffffffffe02404 instr:0x0187b303 iType:Ld [doCommitNormalInst [0]] 8313 +instret:2724 PC:0x1ffff000000000000ffffffffffe02408 instr:0x01e73023 iType:St [doCommitNormalInst [1]] 8313 +instret:2725 PC:0x1ffff000000000000ffffffffffe0240c instr:0x01d73423 iType:St [doCommitNormalInst [0]] 8314 + 83280 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050f80, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h1 } + 83290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 83290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 83290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050f80, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050f88, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f90, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ff0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 83350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f98, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: True, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ff8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2726 PC:0x1ffff000000000000ffffffffffe02410 instr:0x01c73823 iType:St [doCommitNormalInst [0]] 8336 + 83370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fa0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe03000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2727 PC:0x1ffff000000000000ffffffffffe02414 instr:0x00673c23 iType:St [doCommitNormalInst [0]] 8338 +instret:2728 PC:0x1ffff000000000000ffffffffffe02418 instr:0x02078793 iType:Alu [doCommitNormalInst [1]] 8338 + 83390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fa8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2729 PC:0x1ffff000000000000ffffffffffe0241c instr:0x02070713 iType:Alu [doCommitNormalInst [0]] 8340 +instret:2730 PC:0x1ffff000000000000ffffffffffe02420 instr:0xfcb79ce3 iType:Br [doCommitNormalInst [1]] 8340 + 83410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fb0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050fb8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 + 83540 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002440, toState: S, child: } + 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002440, toState: S, child: } + 83550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 83560 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002440, toState: S, child: } ; CRsMsg { addr: 'h0000000080002440, toState: S, data: tagged Invalid , child: } + 83590 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050fc0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h3 } + 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 83600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 83610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 83610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050fc0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fd0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050fd8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050fe0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbe8 } + 83690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050fe8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbec } + 83710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050ff0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf0 } + 83730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 83740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050ff8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbf4 } + 83750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2731 PC:0x1ffff000000000000ffffffffffe02424 instr:0x10089073 iType:Csr [doCommitSystemInst] 8376 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2732 PC:0x1ffff000000000000ffffffffffe02428 instr:0x00361613 iType:Alu [doCommitNormalInst [0]] 8390 +instret:2733 PC:0x1ffff000000000000ffffffffffe0242c instr:0x00c807b3 iType:Alu [doCommitNormalInst [0]] 8391 +instret:2734 PC:0x1ffff000000000000ffffffffffe02430 instr:0x00d7b023 iType:St [doCommitNormalInst [0]] 8392 + 83930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbd0 } + 83940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 83940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbd0 } + 83940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 83950 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080002614, toState: S, child: } + 83960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbd0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007010, fromState: S, toState: M, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080002614, toState: S, child: } + 83960 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 83970 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080002614, toState: S, child: } ; CRsMsg { addr: 'h0000000080002614, toState: S, data: tagged Invalid , child: } + 84030 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007010, toState: M, child: , data: tagged Invalid , id: 'h1 } + 84040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: M, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 84040 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 84040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdbd0 } + 84040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2735 PC:0x1ffff000000000000ffffffffffe02434 instr:0x12050073 iType:SFence [doCommitSystemInst] 8405 +instret:2736 PC:0x1ffff000000000000ffffffffffe02438 instr:0x0000100f iType:FenceI [doCommitSystemInst] 8711 +instret:2737 PC:0x1ffff000000000000ffffffffffe0243c instr:0x00008067 iType:Jr [doCommitNormalInst [0]] 8724 +instret:2738 PC:0x1ffff000000000000ffffffffffe02614 instr:0x00040513 iType:Alu [doCommitNormalInst [0]] 8732 + 87340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 87350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 87350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 87360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 87370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 87370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 87370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 87380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 87380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 87380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } +instret:2739 PC:0x1ffff000000000000ffffffffffe02618 instr:0x06013403 iType:Ld [doCommitNormalInst [0]] 8738 + 87390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } + 87390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } + 87390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09698, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } +instret:2740 PC:0x1ffff000000000000ffffffffffe0261c instr:0x06813083 iType:Ld [doCommitNormalInst [0]] 8739 + 87400 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002640, toState: S, child: } + 87400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } + 87400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } + 87400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2741 PC:0x1ffff000000000000ffffffffffe02620 instr:0x05813483 iType:Ld [doCommitNormalInst [0]] 8740 + 87410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002640, toState: S, child: } + 87410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09688, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } +instret:2742 PC:0x1ffff000000000000ffffffffffe02624 instr:0x05013903 iType:Ld [doCommitNormalInst [0]] 8741 + 87420 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002640, toState: S, child: } ; CRsMsg { addr: 'h0000000080002640, toState: S, data: tagged Invalid , child: } + 87420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } + 87420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } + 87420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } +instret:2743 PC:0x1ffff000000000000ffffffffffe02628 instr:0x04813983 iType:Ld [doCommitNormalInst [0]] 8742 + 87430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } + 87430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } + 87430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 87430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } +instret:2744 PC:0x1ffff000000000000ffffffffffe0262c instr:0x04013a03 iType:Ld [doCommitNormalInst [0]] 8743 + 87440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } + 87440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } + 87440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 87440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } + 87450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } + 87450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } + 87450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2745 PC:0x1ffff000000000000ffffffffffe02630 instr:0x03813a83 iType:Ld [doCommitNormalInst [0]] 8745 +instret:2746 PC:0x1ffff000000000000ffffffffffe02634 instr:0x03013b03 iType:Ld [doCommitNormalInst [0]] 8746 +instret:2747 PC:0x1ffff000000000000ffffffffffe02638 instr:0x02813b83 iType:Ld [doCommitNormalInst [0]] 8747 +instret:2748 PC:0x1ffff000000000000ffffffffffe0263c instr:0x02013c03 iType:Ld [doCommitNormalInst [0]] 8748 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09678, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } + 87570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } + 87570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } + 87570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09668, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } + 87580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } + 87580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } + 87580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 87580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } + 87590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } + 87590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } + 87590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2749 PC:0x1ffff000000000000ffffffffffe02640 instr:0x01813c83 iType:Ld [doCommitNormalInst [0]] 8760 +instret:2750 PC:0x1ffff000000000000ffffffffffe02644 instr:0x01013d03 iType:Ld [doCommitNormalInst [0]] 8761 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2751 PC:0x1ffff000000000000ffffffffffe02648 instr:0x00813d83 iType:Ld [doCommitNormalInst [0]] 8762 +instret:2752 PC:0x1ffff000000000000ffffffffffe0264c instr:0x07010113 iType:Alu [doCommitNormalInst [1]] 8762 + 87630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } +instret:2753 PC:0x1ffff000000000000ffffffffffe02650 instr:0x9f1fd06f iType:J [doCommitNormalInst [0]] 8763 + 87640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } + 87640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } + 87640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2754 PC:0x1ffff000000000000ffffffffffe00040 instr:0x10853283 iType:Ld [doCommitNormalInst [0]] 8767 +instret:2755 PC:0x1ffff000000000000ffffffffffe00044 instr:0x14129073 iType:Scr [doCommitSystemInst] 8773 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 87850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 87850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 87850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 87860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 87860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 87860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 87870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 87870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 87870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 87880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 87880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 87880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } +instret:2756 PC:0x1ffff000000000000ffffffffffe00048 instr:0x00853083 iType:Ld [doCommitNormalInst [0]] 8788 + 87890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } + 87890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } + 87890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09708, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } +instret:2757 PC:0x1ffff000000000000ffffffffffe0004c instr:0x01053103 iType:Ld [doCommitNormalInst [0]] 8789 + 87900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } + 87900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } + 87900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } +instret:2758 PC:0x1ffff000000000000ffffffffffe00050 instr:0x01853183 iType:Ld [doCommitNormalInst [0]] 8790 + 87910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } + 87910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } + 87910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09718, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } +instret:2759 PC:0x1ffff000000000000ffffffffffe00054 instr:0x02053203 iType:Ld [doCommitNormalInst [0]] 8791 + 87920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } + 87920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } + 87920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09728, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } +instret:2760 PC:0x1ffff000000000000ffffffffffe00058 instr:0x02853283 iType:Ld [doCommitNormalInst [0]] 8792 + 87930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } + 87930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } + 87930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } +instret:2761 PC:0x1ffff000000000000ffffffffffe0005c instr:0x03053303 iType:Ld [doCommitNormalInst [0]] 8793 + 87940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } + 87940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } + 87940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09738, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } +instret:2762 PC:0x1ffff000000000000ffffffffffe00060 instr:0x03853383 iType:Ld [doCommitNormalInst [0]] 8794 + 87950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } + 87950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } + 87950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } +instret:2763 PC:0x1ffff000000000000ffffffffffe00064 instr:0x04053403 iType:Ld [doCommitNormalInst [0]] 8795 + 87960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } + 87960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } + 87960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09748, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } +instret:2764 PC:0x1ffff000000000000ffffffffffe00068 instr:0x04853483 iType:Ld [doCommitNormalInst [0]] 8796 + 87970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } + 87970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } + 87970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } +instret:2765 PC:0x1ffff000000000000ffffffffffe0006c instr:0x05853583 iType:Ld [doCommitNormalInst [0]] 8797 + 87980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } + 87980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } + 87980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09758, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } +instret:2766 PC:0x1ffff000000000000ffffffffffe00070 instr:0x06053603 iType:Ld [doCommitNormalInst [0]] 8798 + 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } + 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } + 87990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 87990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } +instret:2767 PC:0x1ffff000000000000ffffffffffe00074 instr:0x06853683 iType:Ld [doCommitNormalInst [0]] 8799 + 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } + 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } + 88000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09768, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } +instret:2768 PC:0x1ffff000000000000ffffffffffe00078 instr:0x07053703 iType:Ld [doCommitNormalInst [0]] 8800 + 88010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } + 88010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } + 88010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } +instret:2769 PC:0x1ffff000000000000ffffffffffe0007c instr:0x07853783 iType:Ld [doCommitNormalInst [0]] 8801 + 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } + 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } + 88020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09778, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } +instret:2770 PC:0x1ffff000000000000ffffffffffe00080 instr:0x08053803 iType:Ld [doCommitNormalInst [0]] 8802 + 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } + 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } + 88030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } +instret:2771 PC:0x1ffff000000000000ffffffffffe00084 instr:0x08853883 iType:Ld [doCommitNormalInst [0]] 8803 + 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } + 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } + 88040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09788, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } +instret:2772 PC:0x1ffff000000000000ffffffffffe00088 instr:0x09053903 iType:Ld [doCommitNormalInst [0]] 8804 + 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } + 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } + 88050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } +instret:2773 PC:0x1ffff000000000000ffffffffffe0008c instr:0x09853983 iType:Ld [doCommitNormalInst [0]] 8805 + 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } + 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } + 88060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09798, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } +instret:2774 PC:0x1ffff000000000000ffffffffffe00090 instr:0x0a053a03 iType:Ld [doCommitNormalInst [0]] 8806 + 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } + 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } + 88070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } +instret:2775 PC:0x1ffff000000000000ffffffffffe00094 instr:0x0a853a83 iType:Ld [doCommitNormalInst [0]] 8807 + 88080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } + 88080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } + 88080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } +instret:2776 PC:0x1ffff000000000000ffffffffffe00098 instr:0x0b053b03 iType:Ld [doCommitNormalInst [0]] 8808 + 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } + 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } + 88090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } +instret:2777 PC:0x1ffff000000000000ffffffffffe0009c instr:0x0b853b83 iType:Ld [doCommitNormalInst [0]] 8809 + 88100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } + 88100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } + 88100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } +instret:2778 PC:0x1ffff000000000000ffffffffffe000a0 instr:0x0c053c03 iType:Ld [doCommitNormalInst [0]] 8810 + 88110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } + 88110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } + 88110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } +instret:2779 PC:0x1ffff000000000000ffffffffffe000a4 instr:0x0c853c83 iType:Ld [doCommitNormalInst [0]] 8811 + 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } + 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } + 88120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } +instret:2780 PC:0x1ffff000000000000ffffffffffe000a8 instr:0x0d053d03 iType:Ld [doCommitNormalInst [0]] 8812 + 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } + 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } + 88130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 88130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } +instret:2781 PC:0x1ffff000000000000ffffffffffe000ac instr:0x0d853d83 iType:Ld [doCommitNormalInst [0]] 8813 + 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } + 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } + 88140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 88140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } +instret:2782 PC:0x1ffff000000000000ffffffffffe000b0 instr:0x0e053e03 iType:Ld [doCommitNormalInst [0]] 8814 + 88150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } + 88150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } + 88150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2783 PC:0x1ffff000000000000ffffffffffe000b4 instr:0x0e853e83 iType:Ld [doCommitNormalInst [0]] 8815 +instret:2784 PC:0x1ffff000000000000ffffffffffe000b8 instr:0x0f053f03 iType:Ld [doCommitNormalInst [0]] 8816 +instret:2785 PC:0x1ffff000000000000ffffffffffe000bc instr:0x0f853f83 iType:Ld [doCommitNormalInst [0]] 8817 +instret:2786 PC:0x1ffff000000000000ffffffffffe000c0 instr:0x05053503 iType:Ld [doCommitNormalInst [0]] 8818 +instret:2787 PC:0x1ffff000000000000ffffffffffe000c4 instr:0x10200073 iType:Sret [doCommitSystemInst] 8820 + 88530 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } + 88540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } + 88540 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 88550 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080007010, toState: S, child: } ; CRsMsg { addr: 'h0000000080007010, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2788 PC:0x1ffff0000000000000000000000002adc instr:0x00000000 iType:Unsupported [doCommitTrap] 8870 +instret:2789 PC:0x1ffff000000000000ffffffffffe000c8 instr:0x14011173 iType:Csr [doCommitSystemInst] 8885 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2790 PC:0x1ffff000000000000ffffffffffe000cc instr:0x00113423 iType:St [doCommitNormalInst [0]] 8897 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 88980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } +instret:2791 PC:0x1ffff000000000000ffffffffffe000d0 instr:0x00313c23 iType:St [doCommitNormalInst [0]] 8898 + 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 88990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09700, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2792 PC:0x1ffff000000000000ffffffffffe000d4 instr:0x02413023 iType:St [doCommitNormalInst [0]] 8899 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09708, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } +instret:2793 PC:0x1ffff000000000000ffffffffffe000d8 instr:0x02513423 iType:St [doCommitNormalInst [0]] 8900 + 89010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 89010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 89010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09710, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2794 PC:0x1ffff000000000000ffffffffffe000dc instr:0x02613823 iType:St [doCommitNormalInst [0]] 8901 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09718, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } +instret:2795 PC:0x1ffff000000000000ffffffffffe000e0 instr:0x02713c23 iType:St [doCommitNormalInst [0]] 8902 + 89030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 89030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 89030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2796 PC:0x1ffff000000000000ffffffffffe000e4 instr:0x04813023 iType:St [doCommitNormalInst [0]] 8903 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09728, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } +instret:2797 PC:0x1ffff000000000000ffffffffffe000e8 instr:0x04913423 iType:St [doCommitNormalInst [0]] 8904 + 89050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 89050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 89050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09730, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2798 PC:0x1ffff000000000000ffffffffffe000ec instr:0x04a13823 iType:St [doCommitNormalInst [0]] 8905 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09738, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } +instret:2799 PC:0x1ffff000000000000ffffffffffe000f0 instr:0x04b13c23 iType:St [doCommitNormalInst [0]] 8906 + 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 89070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09740, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2800 PC:0x1ffff000000000000ffffffffffe000f4 instr:0x06c13023 iType:St [doCommitNormalInst [0]] 8907 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09748, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } +instret:2801 PC:0x1ffff000000000000ffffffffffe000f8 instr:0x06d13423 iType:St [doCommitNormalInst [0]] 8908 + 89090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 89090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 89090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09750, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2802 PC:0x1ffff000000000000ffffffffffe000fc instr:0x06e13823 iType:St [doCommitNormalInst [0]] 8909 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09758, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } +instret:2803 PC:0x1ffff000000000000ffffffffffe00100 instr:0x06f13c23 iType:St [doCommitNormalInst [0]] 8910 + 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 89110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09760, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2804 PC:0x1ffff000000000000ffffffffffe00104 instr:0x09013023 iType:St [doCommitNormalInst [0]] 8911 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09768, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } +instret:2805 PC:0x1ffff000000000000ffffffffffe00108 instr:0x09113423 iType:St [doCommitNormalInst [0]] 8912 + 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 89130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09770, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2806 PC:0x1ffff000000000000ffffffffffe0010c instr:0x09213823 iType:St [doCommitNormalInst [0]] 8913 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09778, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 89140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } +instret:2807 PC:0x1ffff000000000000ffffffffffe00110 instr:0x09313c23 iType:St [doCommitNormalInst [0]] 8914 + 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 89150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09780, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2808 PC:0x1ffff000000000000ffffffffffe00114 instr:0x0b413023 iType:St [doCommitNormalInst [0]] 8915 + 89160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } +instret:2809 PC:0x1ffff000000000000ffffffffffe00118 instr:0x0b513423 iType:St [doCommitNormalInst [0]] 8916 + 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 89170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09788, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2810 PC:0x1ffff000000000000ffffffffffe0011c instr:0x0b613823 iType:St [doCommitNormalInst [0]] 8917 + 89180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 89190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09790, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2811 PC:0x1ffff000000000000ffffffffffe00120 instr:0x0b713c23 iType:St [doCommitNormalInst [0]] 8919 + 89200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 89210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 89210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 89210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09798, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2812 PC:0x1ffff000000000000ffffffffffe00124 instr:0x0d813023 iType:St [doCommitNormalInst [0]] 8921 + 89220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 89230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 89230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 89230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2813 PC:0x1ffff000000000000ffffffffffe00128 instr:0x0d913423 iType:St [doCommitNormalInst [0]] 8923 + 89240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 89250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 89250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 89250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2814 PC:0x1ffff000000000000ffffffffffe0012c instr:0x0da13823 iType:St [doCommitNormalInst [0]] 8925 + 89260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 89270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 89270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 89270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2815 PC:0x1ffff000000000000ffffffffffe00130 instr:0x0db13c23 iType:St [doCommitNormalInst [0]] 8927 + 89280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 89290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 89290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 89290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2816 PC:0x1ffff000000000000ffffffffffe00134 instr:0x0fc13023 iType:St [doCommitNormalInst [0]] 8929 + 89300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 89310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2817 PC:0x1ffff000000000000ffffffffffe00138 instr:0x0fd13423 iType:St [doCommitNormalInst [0]] 8931 + 89320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 89330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2818 PC:0x1ffff000000000000ffffffffffe0013c instr:0x0fe13823 iType:St [doCommitNormalInst [0]] 8933 + 89340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 89350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2819 PC:0x1ffff000000000000ffffffffffe00140 instr:0x0ff13c23 iType:St [doCommitNormalInst [0]] 8935 + 89360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 89370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 89390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 89390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 89390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 89410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 89410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 89410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 89430 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h00000000800025a8, toState: S, child: } + 89430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 89430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 89430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h00000000800025a8, toState: S, child: } + 89440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 89440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 89450 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h00000000800025a8, toState: S, child: } ; CRsMsg { addr: 'h00000000800025a8, toState: S, data: tagged Invalid , child: } + 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 89450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 89470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 89490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 89510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 89530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 89530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 89530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 89550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 89550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 89550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 89570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 89570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 89570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2820 PC:0x1ffff000000000000ffffffffffe00144 instr:0x140112f3 iType:Csr [doCommitSystemInst] 8958 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2821 PC:0x1ffff000000000000ffffffffffe00148 instr:0x00513823 iType:St [doCommitNormalInst [0]] 8970 + 89710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 89720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2822 PC:0x1ffff000000000000ffffffffffe0014c instr:0x100022f3 iType:Csr [doCommitSystemInst] 8976 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2823 PC:0x1ffff000000000000ffffffffffe00150 instr:0x10513023 iType:St [doCommitNormalInst [0]] 8988 +instret:2824 PC:0x1ffff000000000000ffffffffffe00154 instr:0x141022f3 iType:Cap [doCommitNormalInst [1]] 8988 + 89890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } +instret:2825 PC:0x1ffff000000000000ffffffffffe00158 instr:0x10513423 iType:St [doCommitNormalInst [0]] 8989 + 89900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 89900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 89900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 89910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 89920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 89920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 89920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 89920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 89920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2826 PC:0x1ffff000000000000ffffffffffe0015c instr:0x143022f3 iType:Csr [doCommitSystemInst] 8995 + 89980 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h00000000800025c0, toState: S, child: } + 89990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h00000000800025c0, toState: S, child: } + 89990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 90000 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h00000000800025c0, toState: S, child: } ; CRsMsg { addr: 'h00000000800025c0, toState: S, data: tagged Invalid , child: } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2827 PC:0x1ffff000000000000ffffffffffe00160 instr:0x10513823 iType:St [doCommitNormalInst [0]] 9017 + 90180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 90190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2828 PC:0x1ffff000000000000ffffffffffe00164 instr:0x142022f3 iType:Csr [doCommitSystemInst] 9023 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2829 PC:0x1ffff000000000000ffffffffffe00168 instr:0x10513c23 iType:St [doCommitNormalInst [0]] 9035 +instret:2830 PC:0x1ffff000000000000ffffffffffe0016c instr:0x00010513 iType:Alu [doCommitNormalInst [1]] 9035 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 90360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } +instret:2831 PC:0x1ffff000000000000ffffffffffe00170 instr:0x4380206f iType:J [doCommitNormalInst [0]] 9036 + 90370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 90370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 90370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2832 PC:0x1ffff000000000000ffffffffffe025a8 instr:0x11853583 iType:Ld [doCommitNormalInst [0]] 9039 +instret:2833 PC:0x1ffff000000000000ffffffffffe025ac instr:0xf9010113 iType:Alu [doCommitNormalInst [1]] 9039 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2834 PC:0x1ffff000000000000ffffffffffe025b0 instr:0x06813023 iType:St [doCommitNormalInst [0]] 9040 +instret:2835 PC:0x1ffff000000000000ffffffffffe025b4 instr:0x06113423 iType:St [doCommitNormalInst [1]] 9040 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 90410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } +instret:2836 PC:0x1ffff000000000000ffffffffffe025b8 instr:0x04913c23 iType:St [doCommitNormalInst [0]] 9041 +instret:2837 PC:0x1ffff000000000000ffffffffffe025bc instr:0x05213823 iType:St [doCommitNormalInst [1]] 9041 + 90420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 90420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 90420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09698, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2838 PC:0x1ffff000000000000ffffffffffe025c0 instr:0x05313423 iType:St [doCommitNormalInst [0]] 9042 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09690, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 90430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } +instret:2839 PC:0x1ffff000000000000ffffffffffe025c4 instr:0x05413023 iType:St [doCommitNormalInst [0]] 9043 + 90440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 90440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 90440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09688, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2840 PC:0x1ffff000000000000ffffffffffe025c8 instr:0x03513c23 iType:St [doCommitNormalInst [0]] 9044 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09680, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 90450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } +instret:2841 PC:0x1ffff000000000000ffffffffffe025cc instr:0x03613823 iType:St [doCommitNormalInst [0]] 9045 + 90460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 90460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 90460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09678, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2842 PC:0x1ffff000000000000ffffffffffe025d0 instr:0x03713423 iType:St [doCommitNormalInst [0]] 9046 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09670, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 90470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } +instret:2843 PC:0x1ffff000000000000ffffffffffe025d4 instr:0x03813023 iType:St [doCommitNormalInst [0]] 9047 + 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 90480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09668, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2844 PC:0x1ffff000000000000ffffffffffe025d8 instr:0x01913c23 iType:St [doCommitNormalInst [0]] 9048 + 90490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } +instret:2845 PC:0x1ffff000000000000ffffffffffe025dc instr:0x01a13823 iType:St [doCommitNormalInst [0]] 9049 + 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 90500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2846 PC:0x1ffff000000000000ffffffffffe025e0 instr:0x01b13423 iType:St [doCommitNormalInst [0]] 9050 +instret:2847 PC:0x1ffff000000000000ffffffffffe025e4 instr:0x00800793 iType:Alu [doCommitNormalInst [1]] 9050 + 90510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } +instret:2848 PC:0x1ffff000000000000ffffffffffe025e8 instr:0x00050413 iType:Alu [doCommitNormalInst [0]] 9051 +instret:2849 PC:0x1ffff000000000000ffffffffffe025ec instr:0x12f58a63 iType:Br [doCommitNormalInst [1]] 9051 + 90520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 90520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 90520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2850 PC:0x1ffff000000000000ffffffffffe025f0 instr:0x00200793 iType:Alu [doCommitNormalInst [0]] 9052 + 90530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } +instret:2851 PC:0x1ffff000000000000ffffffffffe025f4 instr:0x06f58063 iType:Br [doCommitNormalInst [0]] 9053 + 90540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } + 90540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800097e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9ec } + 90540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 90540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } +instret:2852 PC:0x1ffff000000000000ffffffffffe025f8 instr:0xff458793 iType:Alu [doCommitNormalInst [0]] 9054 +instret:2853 PC:0x1ffff000000000000ffffffffffe025fc instr:0x00100713 iType:Alu [doCommitNormalInst [1]] 9054 + 90550 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002308, toState: S, child: } + 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 90550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2854 PC:0x1ffff000000000000ffffffffffe02600 instr:0x00f77663 iType:Br [doCommitNormalInst [0]] 9055 + 90560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002308, toState: S, child: } + 90560 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 90560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 90570 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002308, toState: S, child: } ; CRsMsg { addr: 'h0000000080002308, toState: S, data: tagged Invalid , child: } + 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 90570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2855 PC:0x1ffff000000000000ffffffffffe0260c instr:0x11043503 iType:Ld [doCommitNormalInst [0]] 9057 +instret:2856 PC:0x1ffff000000000000ffffffffffe02610 instr:0xcf9ff0ef iType:J [doCommitNormalInst [1]] 9057 + 90580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 90590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 90590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 90590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 90600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 90610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 90610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 90610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 90620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 90630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 90630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 90630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 90640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 90650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 90660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 90670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 90670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 90670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 90670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2857 PC:0x1ffff000000000000ffffffffffe02308 instr:0xfffff6b7 iType:Alu [doCommitNormalInst [0]] 9072 +instret:2858 PC:0x1ffff000000000000ffffffffffe0230c instr:0x00d50733 iType:Alu [doCommitNormalInst [0]] 9073 +instret:2859 PC:0x1ffff000000000000ffffffffffe02310 instr:0x0003e7b7 iType:Alu [doCommitNormalInst [1]] 9073 +instret:2860 PC:0x1ffff000000000000ffffffffffe02314 instr:0x14f77463 iType:Br [doCommitNormalInst [0]] 9074 +instret:2861 PC:0x1ffff000000000000ffffffffffe02318 instr:0x00c55893 iType:Alu [doCommitNormalInst [1]] 9074 +instret:2862 PC:0x1ffff000000000000ffffffffffe0231c instr:0x60088613 iType:Alu [doCommitNormalInst [0]] 9075 +instret:2863 PC:0x1ffff000000000000ffffffffffe02320 instr:0x00002817 iType:Auipc [doCommitNormalInst [1]] 9075 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:2864 PC:0x1ffff000000000000ffffffffffe02324 instr:0xce080813 iType:Alu [doCommitNormalInst [0]] 9076 +instret:2865 PC:0x1ffff000000000000ffffffffffe02328 instr:0x00361793 iType:Alu [doCommitNormalInst [1]] 9076 + 90770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } +instret:2866 PC:0x1ffff000000000000ffffffffffe0232c instr:0x00f807b3 iType:Alu [doCommitNormalInst [0]] 9077 + 90780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } + 90780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 90800 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007010, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 90810 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002364, toState: S, child: } + 90820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002364, toState: S, child: } + 90820 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 90830 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002364, toState: S, child: } ; CRsMsg { addr: 'h0000000080002364, toState: S, data: tagged Invalid , child: } + 90870 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007010, toState: E, child: , data: tagged Invalid , id: 'h1 } + 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdcd0 } + 90880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2867 PC:0x1ffff000000000000ffffffffffe02330 instr:0x0007b703 iType:Ld [doCommitNormalInst [0]] 9091 +instret:2868 PC:0x1ffff000000000000ffffffffffe02334 instr:0x00d57533 iType:Alu [doCommitNormalInst [1]] 9091 +instret:2869 PC:0x1ffff000000000000ffffffffffe02338 instr:0x02070663 iType:Br [doCommitNormalInst [0]] 9094 +instret:2870 PC:0x1ffff000000000000ffffffffffe0233c instr:0x04077693 iType:Alu [doCommitNormalInst [0]] 9102 +instret:2871 PC:0x1ffff000000000000ffffffffffe02340 instr:0x10068063 iType:Br [doCommitNormalInst [0]] 9104 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:2872 PC:0x1ffff000000000000ffffffffffe02440 instr:0x04076713 iType:Alu [doCommitNormalInst [0]] 9112 +instret:2873 PC:0x1ffff000000000000ffffffffffe02444 instr:0x00e7b023 iType:St [doCommitNormalInst [0]] 9113 + 91140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdba4 } + 91150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 91150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdba4 } + 91150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 91150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080007010, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdba4 } + 91150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2874 PC:0x1ffff000000000000ffffffffffe02448 instr:0x12050073 iType:SFence [doCommitSystemInst] 9116 +instret:2875 PC:0x1ffff000000000000ffffffffffe0244c instr:0x00008067 iType:Jr [doCommitNormalInst [0]] 9414 +instret:2876 PC:0x1ffff000000000000ffffffffffe02614 instr:0x00040513 iType:Alu [doCommitNormalInst [0]] 9422 + 94240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800096c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9f8 } + 94250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 94250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 94260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 94260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h00000000800096c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9fc } + 94260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 94270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 94270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800096b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c0 } + 94270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h00000000800096b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c4 } + 94280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } +instret:2877 PC:0x1ffff000000000000ffffffffffe02618 instr:0x06013403 iType:Ld [doCommitNormalInst [0]] 9428 + 94290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } + 94290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800096a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9c8 } + 94290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09698, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } +instret:2878 PC:0x1ffff000000000000ffffffffffe0261c instr:0x06813083 iType:Ld [doCommitNormalInst [0]] 9429 + 94300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } + 94300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800096a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9cc } + 94300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } +instret:2879 PC:0x1ffff000000000000ffffffffffe02620 instr:0x05813483 iType:Ld [doCommitNormalInst [0]] 9430 + 94310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } + 94310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d0 } + 94310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09688, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } +instret:2880 PC:0x1ffff000000000000ffffffffffe02624 instr:0x05013903 iType:Ld [doCommitNormalInst [0]] 9431 + 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } + 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d4 } + 94320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } +instret:2881 PC:0x1ffff000000000000ffffffffffe02628 instr:0x04813983 iType:Ld [doCommitNormalInst [0]] 9432 + 94330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } + 94330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9d8 } + 94330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09678, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } +instret:2882 PC:0x1ffff000000000000ffffffffffe0262c instr:0x04013a03 iType:Ld [doCommitNormalInst [0]] 9433 + 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } + 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9dc } + 94340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } +instret:2883 PC:0x1ffff000000000000ffffffffffe02630 instr:0x03813a83 iType:Ld [doCommitNormalInst [0]] 9434 + 94350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } + 94350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a0 } + 94350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09668, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } +instret:2884 PC:0x1ffff000000000000ffffffffffe02634 instr:0x03013b03 iType:Ld [doCommitNormalInst [0]] 9435 + 94360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } + 94360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a4 } + 94360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 94360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } +instret:2885 PC:0x1ffff000000000000ffffffffffe02638 instr:0x02813b83 iType:Ld [doCommitNormalInst [0]] 9436 + 94370 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080007000, toState: S, child: } + 94370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } + 94370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd9a8 } + 94370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2886 PC:0x1ffff000000000000ffffffffffe0263c instr:0x02013c03 iType:Ld [doCommitNormalInst [0]] 9437 + 94380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080007000, toState: S, child: } + 94380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:2887 PC:0x1ffff000000000000ffffffffffe02640 instr:0x01813c83 iType:Ld [doCommitNormalInst [0]] 9438 + 94390 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080007000, toState: S, child: } ; CRsMsg { addr: 'h0000000080007000, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2888 PC:0x1ffff000000000000ffffffffffe02644 instr:0x01013d03 iType:Ld [doCommitNormalInst [0]] 9439 +instret:2889 PC:0x1ffff000000000000ffffffffffe02648 instr:0x00813d83 iType:Ld [doCommitNormalInst [0]] 9440 +instret:2890 PC:0x1ffff000000000000ffffffffffe0264c instr:0x07010113 iType:Alu [doCommitNormalInst [1]] 9440 +instret:2891 PC:0x1ffff000000000000ffffffffffe02650 instr:0x9f1fd06f iType:J [doCommitNormalInst [0]] 9441 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } + 94600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } + 94600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800097d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa0 } + 94600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2892 PC:0x1ffff000000000000ffffffffffe00040 instr:0x10853283 iType:Ld [doCommitNormalInst [0]] 9463 +instret:2893 PC:0x1ffff000000000000ffffffffffe00044 instr:0x14129073 iType:Scr [doCommitSystemInst] 9469 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 94810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 94810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800096d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffa8 } + 94810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 94820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 94820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800096e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffac } + 94820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 94830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 94830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800096e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb0 } + 94830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 94840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 94840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800096f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb4 } + 94840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } +instret:2894 PC:0x1ffff000000000000ffffffffffe00048 instr:0x00853083 iType:Ld [doCommitNormalInst [0]] 9484 + 94850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } + 94850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800096f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffb8 } + 94850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09708, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } +instret:2895 PC:0x1ffff000000000000ffffffffffe0004c instr:0x01053103 iType:Ld [doCommitNormalInst [0]] 9485 + 94860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } + 94860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hffbc } + 94860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } +instret:2896 PC:0x1ffff000000000000ffffffffffe00050 instr:0x01853183 iType:Ld [doCommitNormalInst [0]] 9486 + 94870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } + 94870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff80 } + 94870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09718, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } +instret:2897 PC:0x1ffff000000000000ffffffffffe00054 instr:0x02053203 iType:Ld [doCommitNormalInst [0]] 9487 + 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } + 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080009710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff84 } + 94880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09728, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } +instret:2898 PC:0x1ffff000000000000ffffffffffe00058 instr:0x02853283 iType:Ld [doCommitNormalInst [0]] 9488 + 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } + 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080009718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff88 } + 94890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } +instret:2899 PC:0x1ffff000000000000ffffffffffe0005c instr:0x03053303 iType:Ld [doCommitNormalInst [0]] 9489 + 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } + 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080009728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff8c } + 94900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09738, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } +instret:2900 PC:0x1ffff000000000000ffffffffffe00060 instr:0x03853383 iType:Ld [doCommitNormalInst [0]] 9490 + 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } + 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080009730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff90 } + 94910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } +instret:2901 PC:0x1ffff000000000000ffffffffffe00064 instr:0x04053403 iType:Ld [doCommitNormalInst [0]] 9491 + 94920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } + 94920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080009738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff94 } + 94920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09748, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } +instret:2902 PC:0x1ffff000000000000ffffffffffe00068 instr:0x04853483 iType:Ld [doCommitNormalInst [0]] 9492 + 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } + 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080009740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff98 } + 94930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } +instret:2903 PC:0x1ffff000000000000ffffffffffe0006c instr:0x05853583 iType:Ld [doCommitNormalInst [0]] 9493 + 94940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } + 94940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080009748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff9c } + 94940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09758, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } +instret:2904 PC:0x1ffff000000000000ffffffffffe00070 instr:0x06053603 iType:Ld [doCommitNormalInst [0]] 9494 + 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } + 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080009750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff60 } + 94950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } +instret:2905 PC:0x1ffff000000000000ffffffffffe00074 instr:0x06853683 iType:Ld [doCommitNormalInst [0]] 9495 + 94960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } + 94960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080009758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff64 } + 94960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09768, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } +instret:2906 PC:0x1ffff000000000000ffffffffffe00078 instr:0x07053703 iType:Ld [doCommitNormalInst [0]] 9496 + 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } + 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080009760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff68 } + 94970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } +instret:2907 PC:0x1ffff000000000000ffffffffffe0007c instr:0x07853783 iType:Ld [doCommitNormalInst [0]] 9497 + 94980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } + 94980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080009768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff6c } + 94980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09778, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } +instret:2908 PC:0x1ffff000000000000ffffffffffe00080 instr:0x08053803 iType:Ld [doCommitNormalInst [0]] 9498 + 94990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 94990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } + 94990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 94990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080009770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff70 } + 94990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 94990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } +instret:2909 PC:0x1ffff000000000000ffffffffffe00084 instr:0x08853883 iType:Ld [doCommitNormalInst [0]] 9499 + 95000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } + 95000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080009778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff74 } + 95000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09788, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } +instret:2910 PC:0x1ffff000000000000ffffffffffe00088 instr:0x09053903 iType:Ld [doCommitNormalInst [0]] 9500 + 95010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } + 95010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080009780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff78 } + 95010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } +instret:2911 PC:0x1ffff000000000000ffffffffffe0008c instr:0x09853983 iType:Ld [doCommitNormalInst [0]] 9501 + 95020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } + 95020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080009788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff7c } + 95020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09798, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } +instret:2912 PC:0x1ffff000000000000ffffffffffe00090 instr:0x0a053a03 iType:Ld [doCommitNormalInst [0]] 9502 + 95030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } + 95030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080009790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff40 } + 95030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } +instret:2913 PC:0x1ffff000000000000ffffffffffe00094 instr:0x0a853a83 iType:Ld [doCommitNormalInst [0]] 9503 + 95040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } + 95040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080009798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff44 } + 95040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } +instret:2914 PC:0x1ffff000000000000ffffffffffe00098 instr:0x0b053b03 iType:Ld [doCommitNormalInst [0]] 9504 + 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } + 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h00000000800097a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff48 } + 95050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } +instret:2915 PC:0x1ffff000000000000ffffffffffe0009c instr:0x0b853b83 iType:Ld [doCommitNormalInst [0]] 9505 + 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } + 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h00000000800097a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff4c } + 95060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } +instret:2916 PC:0x1ffff000000000000ffffffffffe000a0 instr:0x0c053c03 iType:Ld [doCommitNormalInst [0]] 9506 + 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } + 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800097b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff50 } + 95070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } +instret:2917 PC:0x1ffff000000000000ffffffffffe000a4 instr:0x0c853c83 iType:Ld [doCommitNormalInst [0]] 9507 + 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } + 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h00000000800097b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff54 } + 95080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } +instret:2918 PC:0x1ffff000000000000ffffffffffe000a8 instr:0x0d053d03 iType:Ld [doCommitNormalInst [0]] 9508 + 95090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } + 95090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h00000000800097c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff58 } + 95090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 95090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } +instret:2919 PC:0x1ffff000000000000ffffffffffe000ac instr:0x0d853d83 iType:Ld [doCommitNormalInst [0]] 9509 + 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } + 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff5c } + 95100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 95100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } +instret:2920 PC:0x1ffff000000000000ffffffffffe000b0 instr:0x0e053e03 iType:Ld [doCommitNormalInst [0]] 9510 + 95110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 95110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } + 95110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 95110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff20 } + 95110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:2921 PC:0x1ffff000000000000ffffffffffe000b4 instr:0x0e853e83 iType:Ld [doCommitNormalInst [0]] 9511 +instret:2922 PC:0x1ffff000000000000ffffffffffe000b8 instr:0x0f053f03 iType:Ld [doCommitNormalInst [0]] 9512 +instret:2923 PC:0x1ffff000000000000ffffffffffe000bc instr:0x0f853f83 iType:Ld [doCommitNormalInst [0]] 9513 +instret:2924 PC:0x1ffff000000000000ffffffffffe000c0 instr:0x05053503 iType:Ld [doCommitNormalInst [0]] 9514 +instret:2925 PC:0x1ffff000000000000ffffffffffe000c4 instr:0x10200073 iType:Sret [doCommitSystemInst] 9516 + 95450 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080050adc, toState: S, child: } + 95460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080050adc, toState: S, child: } + 95460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 95470 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080050adc, toState: S, child: } ; CRsMsg { addr: 'h0000000080050adc, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2926 PC:0x1ffff0000000000000000000000002adc instr:0x00000093 iType:Alu [doCommitNormalInst [0]] 9562 +instret:2927 PC:0x1ffff0000000000000000000000002ae0 instr:0x00000113 iType:Alu [doCommitNormalInst [1]] 9562 +instret:2928 PC:0x1ffff0000000000000000000000002ae4 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9565 +instret:2929 PC:0x1ffff0000000000000000000000002ae8 instr:0x00000e93 iType:Alu [doCommitNormalInst [1]] 9565 +instret:2930 PC:0x1ffff0000000000000000000000002aec instr:0x00200193 iType:Alu [doCommitNormalInst [0]] 9566 + 95690 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080050b00, toState: S, child: } +instret:2931 PC:0x1ffff0000000000000000000000002af0 instr:0x3ddf1263 iType:Br [doCommitNormalInst [0]] 9569 +instret:2932 PC:0x1ffff0000000000000000000000002af4 instr:0x00100093 iType:Alu [doCommitNormalInst [1]] 9569 + 95700 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080050b00, toState: S, child: } + 95700 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:2933 PC:0x1ffff0000000000000000000000002af8 instr:0x00100113 iType:Alu [doCommitNormalInst [0]] 9570 +instret:2934 PC:0x1ffff0000000000000000000000002afc instr:0x02208f3b iType:Alu [doCommitNormalInst [1]] 9570 + 95710 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080050b00, toState: S, child: } ; CRsMsg { addr: 'h0000000080050b00, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2935 PC:0x1ffff0000000000000000000000002b00 instr:0x00100e93 iType:Alu [doCommitNormalInst [0]] 9586 +instret:2936 PC:0x1ffff0000000000000000000000002b04 instr:0x00300193 iType:Alu [doCommitNormalInst [1]] 9586 +instret:2937 PC:0x1ffff0000000000000000000000002b08 instr:0x3bdf1663 iType:Br [doCommitNormalInst [0]] 9587 +instret:2938 PC:0x1ffff0000000000000000000000002b0c instr:0x00300093 iType:Alu [doCommitNormalInst [1]] 9587 +instret:2939 PC:0x1ffff0000000000000000000000002b10 instr:0x00700113 iType:Alu [doCommitNormalInst [0]] 9588 +instret:2940 PC:0x1ffff0000000000000000000000002b14 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9591 +instret:2941 PC:0x1ffff0000000000000000000000002b18 instr:0x01500e93 iType:Alu [doCommitNormalInst [1]] 9591 +instret:2942 PC:0x1ffff0000000000000000000000002b1c instr:0x00400193 iType:Alu [doCommitNormalInst [0]] 9592 +instret:2943 PC:0x1ffff0000000000000000000000002b20 instr:0x39df1a63 iType:Br [doCommitNormalInst [0]] 9595 +instret:2944 PC:0x1ffff0000000000000000000000002b24 instr:0x00000093 iType:Alu [doCommitNormalInst [1]] 9595 + 95960 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080050b40, toState: S, child: } +instret:2945 PC:0x1ffff0000000000000000000000002b28 instr:0xffff8137 iType:Alu [doCommitNormalInst [0]] 9596 +instret:2946 PC:0x1ffff0000000000000000000000002b2c instr:0x02208f3b iType:Alu [doCommitNormalInst [1]] 9596 + 95970 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080050b40, toState: S, child: } + 95970 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:2947 PC:0x1ffff0000000000000000000000002b30 instr:0x00000e93 iType:Alu [doCommitNormalInst [0]] 9597 +instret:2948 PC:0x1ffff0000000000000000000000002b34 instr:0x00500193 iType:Alu [doCommitNormalInst [1]] 9597 + 95980 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080050b40, toState: S, child: } ; CRsMsg { addr: 'h0000000080050b40, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2949 PC:0x1ffff0000000000000000000000002b38 instr:0x37df1e63 iType:Br [doCommitNormalInst [0]] 9598 +instret:2950 PC:0x1ffff0000000000000000000000002b3c instr:0x800000b7 iType:Alu [doCommitNormalInst [1]] 9598 +instret:2951 PC:0x1ffff0000000000000000000000002b40 instr:0x00000113 iType:Alu [doCommitNormalInst [0]] 9613 +instret:2952 PC:0x1ffff0000000000000000000000002b44 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9616 +instret:2953 PC:0x1ffff0000000000000000000000002b48 instr:0x00000e93 iType:Alu [doCommitNormalInst [1]] 9616 +instret:2954 PC:0x1ffff0000000000000000000000002b4c instr:0x00600193 iType:Alu [doCommitNormalInst [0]] 9617 +instret:2955 PC:0x1ffff0000000000000000000000002b50 instr:0x37df1263 iType:Br [doCommitNormalInst [0]] 9620 +instret:2956 PC:0x1ffff0000000000000000000000002b54 instr:0x800000b7 iType:Alu [doCommitNormalInst [1]] 9620 +instret:2957 PC:0x1ffff0000000000000000000000002b58 instr:0xffff8137 iType:Alu [doCommitNormalInst [0]] 9621 +instret:2958 PC:0x1ffff0000000000000000000000002b5c instr:0x02208f3b iType:Alu [doCommitNormalInst [1]] 9621 +instret:2959 PC:0x1ffff0000000000000000000000002b60 instr:0x00000e93 iType:Alu [doCommitNormalInst [0]] 9622 +instret:2960 PC:0x1ffff0000000000000000000000002b64 instr:0x00700193 iType:Alu [doCommitNormalInst [1]] 9622 + 96230 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080050b80, toState: S, child: } +instret:2961 PC:0x1ffff0000000000000000000000002b68 instr:0x35df1663 iType:Br [doCommitNormalInst [0]] 9623 +instret:2962 PC:0x1ffff0000000000000000000000002b6c instr:0x00d00093 iType:Alu [doCommitNormalInst [1]] 9623 + 96240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080050b80, toState: S, child: } + 96240 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:2963 PC:0x1ffff0000000000000000000000002b70 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9624 +instret:2964 PC:0x1ffff0000000000000000000000002b74 instr:0x022080bb iType:Alu [doCommitNormalInst [1]] 9624 + 96250 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080050b80, toState: S, child: } ; CRsMsg { addr: 'h0000000080050b80, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2965 PC:0x1ffff0000000000000000000000002b78 instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 9625 +instret:2966 PC:0x1ffff0000000000000000000000002b7c instr:0x00800193 iType:Alu [doCommitNormalInst [1]] 9625 +instret:2967 PC:0x1ffff0000000000000000000000002b80 instr:0x33d09a63 iType:Br [doCommitNormalInst [0]] 9640 +instret:2968 PC:0x1ffff0000000000000000000000002b84 instr:0x00e00093 iType:Alu [doCommitNormalInst [1]] 9640 +instret:2969 PC:0x1ffff0000000000000000000000002b88 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9641 +instret:2970 PC:0x1ffff0000000000000000000000002b8c instr:0x0220813b iType:Alu [doCommitNormalInst [0]] 9644 +instret:2971 PC:0x1ffff0000000000000000000000002b90 instr:0x09a00e93 iType:Alu [doCommitNormalInst [1]] 9644 +instret:2972 PC:0x1ffff0000000000000000000000002b94 instr:0x00900193 iType:Alu [doCommitNormalInst [0]] 9645 +instret:2973 PC:0x1ffff0000000000000000000000002b98 instr:0x31d11e63 iType:Br [doCommitNormalInst [0]] 9648 +instret:2974 PC:0x1ffff0000000000000000000000002b9c instr:0x00d00093 iType:Alu [doCommitNormalInst [1]] 9648 +instret:2975 PC:0x1ffff0000000000000000000000002ba0 instr:0x021080bb iType:Alu [doCommitNormalInst [0]] 9649 +instret:2976 PC:0x1ffff0000000000000000000000002ba4 instr:0x0a900e93 iType:Alu [doCommitNormalInst [1]] 9649 + 96500 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080050bc0, toState: S, child: } +instret:2977 PC:0x1ffff0000000000000000000000002ba8 instr:0x00a00193 iType:Alu [doCommitNormalInst [0]] 9650 +instret:2978 PC:0x1ffff0000000000000000000000002bac instr:0x31d09463 iType:Br [doCommitNormalInst [1]] 9650 + 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080050bc0, toState: S, child: } + 96510 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:2979 PC:0x1ffff0000000000000000000000002bb0 instr:0x00000213 iType:Alu [doCommitNormalInst [0]] 9651 +instret:2980 PC:0x1ffff0000000000000000000000002bb4 instr:0x00d00093 iType:Alu [doCommitNormalInst [1]] 9651 + 96520 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080050bc0, toState: S, child: } ; CRsMsg { addr: 'h0000000080050bc0, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2981 PC:0x1ffff0000000000000000000000002bb8 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9652 +instret:2982 PC:0x1ffff0000000000000000000000002bbc instr:0x02208f3b iType:Alu [doCommitNormalInst [1]] 9652 +instret:2983 PC:0x1ffff0000000000000000000000002bc0 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9667 +instret:2984 PC:0x1ffff0000000000000000000000002bc4 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9667 +instret:2985 PC:0x1ffff0000000000000000000000002bc8 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9668 +instret:2986 PC:0x1ffff0000000000000000000000002bcc instr:0xfe5214e3 iType:Br [doCommitNormalInst [0]] 9670 + 96770 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080050c00, toState: S, child: } + 96780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080050c00, toState: S, child: } + 96780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 96790 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080050c00, toState: S, child: } ; CRsMsg { addr: 'h0000000080050c00, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:2987 PC:0x1ffff0000000000000000000000002bb4 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 9696 +instret:2988 PC:0x1ffff0000000000000000000000002bb8 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9696 +instret:2989 PC:0x1ffff0000000000000000000000002bbc instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9699 +instret:2990 PC:0x1ffff0000000000000000000000002bc0 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9704 +instret:2991 PC:0x1ffff0000000000000000000000002bc4 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9704 +instret:2992 PC:0x1ffff0000000000000000000000002bc8 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9705 +instret:2993 PC:0x1ffff0000000000000000000000002bcc instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9705 +instret:2994 PC:0x1ffff0000000000000000000000002bd0 instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 9709 +instret:2995 PC:0x1ffff0000000000000000000000002bd4 instr:0x00b00193 iType:Alu [doCommitNormalInst [1]] 9709 +instret:2996 PC:0x1ffff0000000000000000000000002bd8 instr:0x2dd31e63 iType:Br [doCommitNormalInst [0]] 9710 +instret:2997 PC:0x1ffff0000000000000000000000002bdc instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9710 +instret:2998 PC:0x1ffff0000000000000000000000002be0 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9711 +instret:2999 PC:0x1ffff0000000000000000000000002be4 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9711 +instret:3000 PC:0x1ffff0000000000000000000000002be8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9714 +instret:3001 PC:0x1ffff0000000000000000000000002bec instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9714 +instret:3002 PC:0x1ffff0000000000000000000000002bf0 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9719 +instret:3003 PC:0x1ffff0000000000000000000000002bf4 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9719 +instret:3004 PC:0x1ffff0000000000000000000000002bf8 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9720 +instret:3005 PC:0x1ffff0000000000000000000000002bfc instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9720 +instret:3006 PC:0x1ffff0000000000000000000000002be0 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9724 +instret:3007 PC:0x1ffff0000000000000000000000002be4 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9724 +instret:3008 PC:0x1ffff0000000000000000000000002be8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9727 +instret:3009 PC:0x1ffff0000000000000000000000002bec instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9727 +instret:3010 PC:0x1ffff0000000000000000000000002bf0 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9731 +instret:3011 PC:0x1ffff0000000000000000000000002bf4 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9731 +instret:3012 PC:0x1ffff0000000000000000000000002bf8 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9732 +instret:3013 PC:0x1ffff0000000000000000000000002bfc instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9732 +instret:3014 PC:0x1ffff0000000000000000000000002c00 instr:0x09a00e93 iType:Alu [doCommitNormalInst [0]] 9733 +instret:3015 PC:0x1ffff0000000000000000000000002c04 instr:0x00c00193 iType:Alu [doCommitNormalInst [1]] 9733 +instret:3016 PC:0x1ffff0000000000000000000000002c08 instr:0x2bd31663 iType:Br [doCommitNormalInst [0]] 9734 +instret:3017 PC:0x1ffff0000000000000000000000002c0c instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9734 +instret:3018 PC:0x1ffff0000000000000000000000002c10 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9735 +instret:3019 PC:0x1ffff0000000000000000000000002c14 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9735 +instret:3020 PC:0x1ffff0000000000000000000000002c18 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9737 +instret:3021 PC:0x1ffff0000000000000000000000002c1c instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9737 +instret:3022 PC:0x1ffff0000000000000000000000002c20 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9738 + 97400 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080050c40, toState: S, child: } + 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080050c40, toState: S, child: } + 97410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:3023 PC:0x1ffff0000000000000000000000002c24 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9741 +instret:3024 PC:0x1ffff0000000000000000000000002c28 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9741 + 97420 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080050c40, toState: S, child: } ; CRsMsg { addr: 'h0000000080050c40, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3025 PC:0x1ffff0000000000000000000000002c2c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9742 +instret:3026 PC:0x1ffff0000000000000000000000002c30 instr:0xfe5210e3 iType:Br [doCommitNormalInst [1]] 9742 +instret:3027 PC:0x1ffff0000000000000000000000002c10 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9759 +instret:3028 PC:0x1ffff0000000000000000000000002c14 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9759 +instret:3029 PC:0x1ffff0000000000000000000000002c18 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9762 +instret:3030 PC:0x1ffff0000000000000000000000002c1c instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9762 +instret:3031 PC:0x1ffff0000000000000000000000002c20 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9763 +instret:3032 PC:0x1ffff0000000000000000000000002c24 instr:0x000f0313 iType:Alu [doCommitNormalInst [0]] 9766 +instret:3033 PC:0x1ffff0000000000000000000000002c28 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9766 +instret:3034 PC:0x1ffff0000000000000000000000002c2c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9767 +instret:3035 PC:0x1ffff0000000000000000000000002c30 instr:0xfe5210e3 iType:Br [doCommitNormalInst [1]] 9767 +instret:3036 PC:0x1ffff0000000000000000000000002c34 instr:0x0a500e93 iType:Alu [doCommitNormalInst [0]] 9768 +instret:3037 PC:0x1ffff0000000000000000000000002c38 instr:0x00d00193 iType:Alu [doCommitNormalInst [1]] 9768 +instret:3038 PC:0x1ffff0000000000000000000000002c3c instr:0x27d31c63 iType:Br [doCommitNormalInst [0]] 9769 +instret:3039 PC:0x1ffff0000000000000000000000002c40 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9769 +instret:3040 PC:0x1ffff0000000000000000000000002c44 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 9770 +instret:3041 PC:0x1ffff0000000000000000000000002c48 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9770 +instret:3042 PC:0x1ffff0000000000000000000000002c4c instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9772 +instret:3043 PC:0x1ffff0000000000000000000000002c50 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9772 +instret:3044 PC:0x1ffff0000000000000000000000002c54 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9773 +instret:3045 PC:0x1ffff0000000000000000000000002c58 instr:0xfe5216e3 iType:Br [doCommitNormalInst [1]] 9773 + 97780 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080050c80, toState: S, child: } + 97790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080050c80, toState: S, child: } + 97790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 97800 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080050c80, toState: S, child: } ; CRsMsg { addr: 'h0000000080050c80, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3046 PC:0x1ffff0000000000000000000000002c44 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 9797 +instret:3047 PC:0x1ffff0000000000000000000000002c48 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9797 +instret:3048 PC:0x1ffff0000000000000000000000002c4c instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9800 +instret:3049 PC:0x1ffff0000000000000000000000002c50 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9800 +instret:3050 PC:0x1ffff0000000000000000000000002c54 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9801 +instret:3051 PC:0x1ffff0000000000000000000000002c58 instr:0xfe5216e3 iType:Br [doCommitNormalInst [1]] 9801 +instret:3052 PC:0x1ffff0000000000000000000000002c5c instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 9802 +instret:3053 PC:0x1ffff0000000000000000000000002c60 instr:0x00e00193 iType:Alu [doCommitNormalInst [1]] 9802 +instret:3054 PC:0x1ffff0000000000000000000000002c64 instr:0x25df1863 iType:Br [doCommitNormalInst [0]] 9804 +instret:3055 PC:0x1ffff0000000000000000000000002c68 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9804 +instret:3056 PC:0x1ffff0000000000000000000000002c6c instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9805 +instret:3057 PC:0x1ffff0000000000000000000000002c70 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9805 +instret:3058 PC:0x1ffff0000000000000000000000002c74 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9806 +instret:3059 PC:0x1ffff0000000000000000000000002c78 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9809 +instret:3060 PC:0x1ffff0000000000000000000000002c7c instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9809 +instret:3061 PC:0x1ffff0000000000000000000000002c80 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9810 +instret:3062 PC:0x1ffff0000000000000000000000002c84 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9810 + 98170 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080050cc0, toState: S, child: } + 98180 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080050cc0, toState: S, child: } + 98180 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 98190 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080050cc0, toState: S, child: } ; CRsMsg { addr: 'h0000000080050cc0, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3063 PC:0x1ffff0000000000000000000000002c6c instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9835 +instret:3064 PC:0x1ffff0000000000000000000000002c70 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9835 +instret:3065 PC:0x1ffff0000000000000000000000002c74 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9836 +instret:3066 PC:0x1ffff0000000000000000000000002c78 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9838 +instret:3067 PC:0x1ffff0000000000000000000000002c7c instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9838 +instret:3068 PC:0x1ffff0000000000000000000000002c80 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9839 +instret:3069 PC:0x1ffff0000000000000000000000002c84 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9839 +instret:3070 PC:0x1ffff0000000000000000000000002c88 instr:0x09a00e93 iType:Alu [doCommitNormalInst [0]] 9841 +instret:3071 PC:0x1ffff0000000000000000000000002c8c instr:0x00f00193 iType:Alu [doCommitNormalInst [1]] 9841 +instret:3072 PC:0x1ffff0000000000000000000000002c90 instr:0x23df1263 iType:Br [doCommitNormalInst [0]] 9842 +instret:3073 PC:0x1ffff0000000000000000000000002c94 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9842 +instret:3074 PC:0x1ffff0000000000000000000000002c98 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9843 +instret:3075 PC:0x1ffff0000000000000000000000002c9c instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9843 +instret:3076 PC:0x1ffff0000000000000000000000002ca0 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9844 +instret:3077 PC:0x1ffff0000000000000000000000002ca4 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9844 +instret:3078 PC:0x1ffff0000000000000000000000002ca8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9848 +instret:3079 PC:0x1ffff0000000000000000000000002cac instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9848 +instret:3080 PC:0x1ffff0000000000000000000000002cb0 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9849 +instret:3081 PC:0x1ffff0000000000000000000000002cb4 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9849 +instret:3082 PC:0x1ffff0000000000000000000000002c98 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9856 +instret:3083 PC:0x1ffff0000000000000000000000002c9c instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9856 +instret:3084 PC:0x1ffff0000000000000000000000002ca0 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9857 +instret:3085 PC:0x1ffff0000000000000000000000002ca4 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9857 +instret:3086 PC:0x1ffff0000000000000000000000002ca8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9860 +instret:3087 PC:0x1ffff0000000000000000000000002cac instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9860 +instret:3088 PC:0x1ffff0000000000000000000000002cb0 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9861 +instret:3089 PC:0x1ffff0000000000000000000000002cb4 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9861 +instret:3090 PC:0x1ffff0000000000000000000000002cb8 instr:0x0a500e93 iType:Alu [doCommitNormalInst [0]] 9862 +instret:3091 PC:0x1ffff0000000000000000000000002cbc instr:0x01000193 iType:Alu [doCommitNormalInst [1]] 9862 +instret:3092 PC:0x1ffff0000000000000000000000002cc0 instr:0x1fdf1a63 iType:Br [doCommitNormalInst [0]] 9864 +instret:3093 PC:0x1ffff0000000000000000000000002cc4 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9864 +instret:3094 PC:0x1ffff0000000000000000000000002cc8 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 9865 +instret:3095 PC:0x1ffff0000000000000000000000002ccc instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9865 +instret:3096 PC:0x1ffff0000000000000000000000002cd0 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9866 +instret:3097 PC:0x1ffff0000000000000000000000002cd4 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9869 +instret:3098 PC:0x1ffff0000000000000000000000002cd8 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9869 +instret:3099 PC:0x1ffff0000000000000000000000002cdc instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9870 +instret:3100 PC:0x1ffff0000000000000000000000002ce0 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9870 +instret:3101 PC:0x1ffff0000000000000000000000002cc8 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 9871 +instret:3102 PC:0x1ffff0000000000000000000000002ccc instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9871 +instret:3103 PC:0x1ffff0000000000000000000000002cd0 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9872 +instret:3104 PC:0x1ffff0000000000000000000000002cd4 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9874 +instret:3105 PC:0x1ffff0000000000000000000000002cd8 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9874 +instret:3106 PC:0x1ffff0000000000000000000000002cdc instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9875 +instret:3107 PC:0x1ffff0000000000000000000000002ce0 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9875 +instret:3108 PC:0x1ffff0000000000000000000000002ce4 instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 9876 +instret:3109 PC:0x1ffff0000000000000000000000002ce8 instr:0x01100193 iType:Alu [doCommitNormalInst [1]] 9876 +instret:3110 PC:0x1ffff0000000000000000000000002cec instr:0x1ddf1463 iType:Br [doCommitNormalInst [0]] 9878 +instret:3111 PC:0x1ffff0000000000000000000000002cf0 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9878 +instret:3112 PC:0x1ffff0000000000000000000000002cf4 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9879 +instret:3113 PC:0x1ffff0000000000000000000000002cf8 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9879 +instret:3114 PC:0x1ffff0000000000000000000000002cfc instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9880 + 98820 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080050d00, toState: S, child: } + 98830 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080050d00, toState: S, child: } + 98830 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 98840 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080050d00, toState: S, child: } ; CRsMsg { addr: 'h0000000080050d00, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3115 PC:0x1ffff0000000000000000000000002d00 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9899 +instret:3116 PC:0x1ffff0000000000000000000000002d04 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9901 +instret:3117 PC:0x1ffff0000000000000000000000002d08 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9901 +instret:3118 PC:0x1ffff0000000000000000000000002d0c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9902 +instret:3119 PC:0x1ffff0000000000000000000000002d10 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9902 +instret:3120 PC:0x1ffff0000000000000000000000002cf4 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9904 +instret:3121 PC:0x1ffff0000000000000000000000002cf8 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9904 +instret:3122 PC:0x1ffff0000000000000000000000002cfc instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9905 +instret:3123 PC:0x1ffff0000000000000000000000002d00 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9906 +instret:3124 PC:0x1ffff0000000000000000000000002d04 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9908 +instret:3125 PC:0x1ffff0000000000000000000000002d08 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9908 +instret:3126 PC:0x1ffff0000000000000000000000002d0c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9909 +instret:3127 PC:0x1ffff0000000000000000000000002d10 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9909 +instret:3128 PC:0x1ffff0000000000000000000000002d14 instr:0x09a00e93 iType:Alu [doCommitNormalInst [0]] 9911 +instret:3129 PC:0x1ffff0000000000000000000000002d18 instr:0x01200193 iType:Alu [doCommitNormalInst [1]] 9911 +instret:3130 PC:0x1ffff0000000000000000000000002d1c instr:0x19df1c63 iType:Br [doCommitNormalInst [0]] 9912 +instret:3131 PC:0x1ffff0000000000000000000000002d20 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9912 +instret:3132 PC:0x1ffff0000000000000000000000002d24 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9913 +instret:3133 PC:0x1ffff0000000000000000000000002d28 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9913 +instret:3134 PC:0x1ffff0000000000000000000000002d2c instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9914 +instret:3135 PC:0x1ffff0000000000000000000000002d30 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9914 +instret:3136 PC:0x1ffff0000000000000000000000002d34 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9917 +instret:3137 PC:0x1ffff0000000000000000000000002d38 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9917 +instret:3138 PC:0x1ffff0000000000000000000000002d3c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9918 + 99190 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080050d40, toState: S, child: } + 99200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080050d40, toState: S, child: } + 99200 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 99210 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080050d40, toState: S, child: } ; CRsMsg { addr: 'h0000000080050d40, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3139 PC:0x1ffff0000000000000000000000002d40 instr:0xfe5212e3 iType:Br [doCommitNormalInst [0]] 9936 +instret:3140 PC:0x1ffff0000000000000000000000002d24 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 9939 +instret:3141 PC:0x1ffff0000000000000000000000002d28 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9939 +instret:3142 PC:0x1ffff0000000000000000000000002d2c instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9940 +instret:3143 PC:0x1ffff0000000000000000000000002d30 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 9940 +instret:3144 PC:0x1ffff0000000000000000000000002d34 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9943 +instret:3145 PC:0x1ffff0000000000000000000000002d38 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9943 +instret:3146 PC:0x1ffff0000000000000000000000002d3c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9944 +instret:3147 PC:0x1ffff0000000000000000000000002d40 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 9944 +instret:3148 PC:0x1ffff0000000000000000000000002d44 instr:0x0a500e93 iType:Alu [doCommitNormalInst [0]] 9946 +instret:3149 PC:0x1ffff0000000000000000000000002d48 instr:0x01300193 iType:Alu [doCommitNormalInst [1]] 9946 +instret:3150 PC:0x1ffff0000000000000000000000002d4c instr:0x17df1463 iType:Br [doCommitNormalInst [0]] 9947 +instret:3151 PC:0x1ffff0000000000000000000000002d50 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9947 +instret:3152 PC:0x1ffff0000000000000000000000002d54 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9948 +instret:3153 PC:0x1ffff0000000000000000000000002d58 instr:0x00d00093 iType:Alu [doCommitNormalInst [1]] 9948 +instret:3154 PC:0x1ffff0000000000000000000000002d5c instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9951 +instret:3155 PC:0x1ffff0000000000000000000000002d60 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9951 +instret:3156 PC:0x1ffff0000000000000000000000002d64 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9952 +instret:3157 PC:0x1ffff0000000000000000000000002d68 instr:0xfe5216e3 iType:Br [doCommitNormalInst [1]] 9952 +instret:3158 PC:0x1ffff0000000000000000000000002d54 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9953 +instret:3159 PC:0x1ffff0000000000000000000000002d58 instr:0x00d00093 iType:Alu [doCommitNormalInst [1]] 9953 +instret:3160 PC:0x1ffff0000000000000000000000002d5c instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9956 +instret:3161 PC:0x1ffff0000000000000000000000002d60 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9956 +instret:3162 PC:0x1ffff0000000000000000000000002d64 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9957 +instret:3163 PC:0x1ffff0000000000000000000000002d68 instr:0xfe5216e3 iType:Br [doCommitNormalInst [1]] 9957 +instret:3164 PC:0x1ffff0000000000000000000000002d6c instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 9958 +instret:3165 PC:0x1ffff0000000000000000000000002d70 instr:0x01400193 iType:Alu [doCommitNormalInst [1]] 9958 +instret:3166 PC:0x1ffff0000000000000000000000002d74 instr:0x15df1063 iType:Br [doCommitNormalInst [0]] 9960 +instret:3167 PC:0x1ffff0000000000000000000000002d78 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9960 +instret:3168 PC:0x1ffff0000000000000000000000002d7c instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9961 + 99630 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080050d80, toState: S, child: } + 99640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080050d80, toState: S, child: } + 99640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 99650 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080050d80, toState: S, child: } ; CRsMsg { addr: 'h0000000080050d80, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3169 PC:0x1ffff0000000000000000000000002d80 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9980 +instret:3170 PC:0x1ffff0000000000000000000000002d84 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9980 +instret:3171 PC:0x1ffff0000000000000000000000002d88 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9983 +instret:3172 PC:0x1ffff0000000000000000000000002d8c instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9983 +instret:3173 PC:0x1ffff0000000000000000000000002d90 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9984 +instret:3174 PC:0x1ffff0000000000000000000000002d94 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9984 +instret:3175 PC:0x1ffff0000000000000000000000002d7c instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9985 +instret:3176 PC:0x1ffff0000000000000000000000002d80 instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 9986 +instret:3177 PC:0x1ffff0000000000000000000000002d84 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9986 +instret:3178 PC:0x1ffff0000000000000000000000002d88 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9989 +instret:3179 PC:0x1ffff0000000000000000000000002d8c instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9989 +instret:3180 PC:0x1ffff0000000000000000000000002d90 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 9990 +instret:3181 PC:0x1ffff0000000000000000000000002d94 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 9990 +instret:3182 PC:0x1ffff0000000000000000000000002d98 instr:0x09a00e93 iType:Alu [doCommitNormalInst [0]] 9991 +instret:3183 PC:0x1ffff0000000000000000000000002d9c instr:0x01500193 iType:Alu [doCommitNormalInst [1]] 9991 +instret:3184 PC:0x1ffff0000000000000000000000002da0 instr:0x11df1a63 iType:Br [doCommitNormalInst [0]] 9993 +instret:3185 PC:0x1ffff0000000000000000000000002da4 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 9993 +instret:3186 PC:0x1ffff0000000000000000000000002da8 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 9994 +instret:3187 PC:0x1ffff0000000000000000000000002dac instr:0x00f00093 iType:Alu [doCommitNormalInst [1]] 9994 +instret:3188 PC:0x1ffff0000000000000000000000002db0 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 9995 +instret:3189 PC:0x1ffff0000000000000000000000002db4 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 9995 +instret:3190 PC:0x1ffff0000000000000000000000002db8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 9997 +instret:3191 PC:0x1ffff0000000000000000000000002dbc instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 9997 + 99980 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080050dc0, toState: S, child: } + 99990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080050dc0, toState: S, child: } + 99990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 100000 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080050dc0, toState: S, child: } ; CRsMsg { addr: 'h0000000080050dc0, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3192 PC:0x1ffff0000000000000000000000002dc0 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10015 +instret:3193 PC:0x1ffff0000000000000000000000002dc4 instr:0xfe5212e3 iType:Br [doCommitNormalInst [0]] 10016 +instret:3194 PC:0x1ffff0000000000000000000000002da8 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10018 +instret:3195 PC:0x1ffff0000000000000000000000002dac instr:0x00f00093 iType:Alu [doCommitNormalInst [1]] 10018 +instret:3196 PC:0x1ffff0000000000000000000000002db0 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 10019 +instret:3197 PC:0x1ffff0000000000000000000000002db4 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10019 +instret:3198 PC:0x1ffff0000000000000000000000002db8 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10022 +instret:3199 PC:0x1ffff0000000000000000000000002dbc instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10022 +instret:3200 PC:0x1ffff0000000000000000000000002dc0 instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10023 +instret:3201 PC:0x1ffff0000000000000000000000002dc4 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 10023 +instret:3202 PC:0x1ffff0000000000000000000000002dc8 instr:0x0a500e93 iType:Alu [doCommitNormalInst [0]] 10024 +instret:3203 PC:0x1ffff0000000000000000000000002dcc instr:0x01600193 iType:Alu [doCommitNormalInst [1]] 10024 +instret:3204 PC:0x1ffff0000000000000000000000002dd0 instr:0x0fdf1263 iType:Br [doCommitNormalInst [0]] 10026 +instret:3205 PC:0x1ffff0000000000000000000000002dd4 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 10026 +instret:3206 PC:0x1ffff0000000000000000000000002dd8 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10027 +instret:3207 PC:0x1ffff0000000000000000000000002ddc instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10027 +instret:3208 PC:0x1ffff0000000000000000000000002de0 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 10028 +instret:3209 PC:0x1ffff0000000000000000000000002de4 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10031 +instret:3210 PC:0x1ffff0000000000000000000000002de8 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10031 +instret:3211 PC:0x1ffff0000000000000000000000002dec instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10032 +instret:3212 PC:0x1ffff0000000000000000000000002df0 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 10032 + 100330 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080050e00, toState: S, child: } + 100340 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080050e00, toState: S, child: } + 100340 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 100350 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080050e00, toState: S, child: } ; CRsMsg { addr: 'h0000000080050e00, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3213 PC:0x1ffff0000000000000000000000002dd8 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10051 +instret:3214 PC:0x1ffff0000000000000000000000002ddc instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10051 +instret:3215 PC:0x1ffff0000000000000000000000002de0 instr:0x00d00093 iType:Alu [doCommitNormalInst [0]] 10052 +instret:3216 PC:0x1ffff0000000000000000000000002de4 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10055 +instret:3217 PC:0x1ffff0000000000000000000000002de8 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10055 +instret:3218 PC:0x1ffff0000000000000000000000002dec instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10056 +instret:3219 PC:0x1ffff0000000000000000000000002df0 instr:0xfe5214e3 iType:Br [doCommitNormalInst [1]] 10056 +instret:3220 PC:0x1ffff0000000000000000000000002df4 instr:0x08f00e93 iType:Alu [doCommitNormalInst [0]] 10057 +instret:3221 PC:0x1ffff0000000000000000000000002df8 instr:0x01700193 iType:Alu [doCommitNormalInst [1]] 10057 +instret:3222 PC:0x1ffff0000000000000000000000002dfc instr:0x0bdf1c63 iType:Br [doCommitNormalInst [0]] 10059 +instret:3223 PC:0x1ffff0000000000000000000000002e00 instr:0x00000213 iType:Alu [doCommitNormalInst [0]] 10060 +instret:3224 PC:0x1ffff0000000000000000000000002e04 instr:0x00b00113 iType:Alu [doCommitNormalInst [1]] 10060 +instret:3225 PC:0x1ffff0000000000000000000000002e08 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 10061 +instret:3226 PC:0x1ffff0000000000000000000000002e0c instr:0x00e00093 iType:Alu [doCommitNormalInst [1]] 10061 +instret:3227 PC:0x1ffff0000000000000000000000002e10 instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 10062 +instret:3228 PC:0x1ffff0000000000000000000000002e14 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10064 +instret:3229 PC:0x1ffff0000000000000000000000002e18 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10064 +instret:3230 PC:0x1ffff0000000000000000000000002e1c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10065 +instret:3231 PC:0x1ffff0000000000000000000000002e20 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 10065 +instret:3232 PC:0x1ffff0000000000000000000000002e04 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10066 +instret:3233 PC:0x1ffff0000000000000000000000002e08 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10066 +instret:3234 PC:0x1ffff0000000000000000000000002e0c instr:0x00e00093 iType:Alu [doCommitNormalInst [0]] 10067 +instret:3235 PC:0x1ffff0000000000000000000000002e10 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10067 +instret:3236 PC:0x1ffff0000000000000000000000002e14 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10070 +instret:3237 PC:0x1ffff0000000000000000000000002e18 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10070 +instret:3238 PC:0x1ffff0000000000000000000000002e1c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10071 +instret:3239 PC:0x1ffff0000000000000000000000002e20 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 10071 +instret:3240 PC:0x1ffff0000000000000000000000002e24 instr:0x09a00e93 iType:Alu [doCommitNormalInst [0]] 10072 +instret:3241 PC:0x1ffff0000000000000000000000002e28 instr:0x01800193 iType:Alu [doCommitNormalInst [1]] 10072 +instret:3242 PC:0x1ffff0000000000000000000000002e2c instr:0x09df1463 iType:Br [doCommitNormalInst [0]] 10074 +instret:3243 PC:0x1ffff0000000000000000000000002e30 instr:0x00000213 iType:Alu [doCommitNormalInst [1]] 10074 +instret:3244 PC:0x1ffff0000000000000000000000002e34 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10075 +instret:3245 PC:0x1ffff0000000000000000000000002e38 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10075 +instret:3246 PC:0x1ffff0000000000000000000000002e3c instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 10076 + 100780 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080050e40, toState: S, child: } + 100790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080050e40, toState: S, child: } + 100790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 100800 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080050e40, toState: S, child: } ; CRsMsg { addr: 'h0000000080050e40, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3247 PC:0x1ffff0000000000000000000000002e40 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 10095 +instret:3248 PC:0x1ffff0000000000000000000000002e44 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10098 +instret:3249 PC:0x1ffff0000000000000000000000002e48 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10098 +instret:3250 PC:0x1ffff0000000000000000000000002e4c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10099 +instret:3251 PC:0x1ffff0000000000000000000000002e50 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 10099 +instret:3252 PC:0x1ffff0000000000000000000000002e34 instr:0x00b00113 iType:Alu [doCommitNormalInst [0]] 10100 +instret:3253 PC:0x1ffff0000000000000000000000002e38 instr:0x00000013 iType:Alu [doCommitNormalInst [1]] 10100 +instret:3254 PC:0x1ffff0000000000000000000000002e3c instr:0x00000013 iType:Alu [doCommitNormalInst [0]] 10101 +instret:3255 PC:0x1ffff0000000000000000000000002e40 instr:0x00f00093 iType:Alu [doCommitNormalInst [0]] 10102 +instret:3256 PC:0x1ffff0000000000000000000000002e44 instr:0x02208f3b iType:Alu [doCommitNormalInst [0]] 10105 +instret:3257 PC:0x1ffff0000000000000000000000002e48 instr:0x00120213 iType:Alu [doCommitNormalInst [1]] 10105 +instret:3258 PC:0x1ffff0000000000000000000000002e4c instr:0x00200293 iType:Alu [doCommitNormalInst [0]] 10106 +instret:3259 PC:0x1ffff0000000000000000000000002e50 instr:0xfe5212e3 iType:Br [doCommitNormalInst [1]] 10106 +instret:3260 PC:0x1ffff0000000000000000000000002e54 instr:0x0a500e93 iType:Alu [doCommitNormalInst [0]] 10107 +instret:3261 PC:0x1ffff0000000000000000000000002e58 instr:0x01900193 iType:Alu [doCommitNormalInst [1]] 10107 +instret:3262 PC:0x1ffff0000000000000000000000002e5c instr:0x05df1c63 iType:Br [doCommitNormalInst [0]] 10109 +instret:3263 PC:0x1ffff0000000000000000000000002e60 instr:0x01f00093 iType:Alu [doCommitNormalInst [1]] 10109 +instret:3264 PC:0x1ffff0000000000000000000000002e64 instr:0x0210013b iType:Alu [doCommitNormalInst [0]] 10111 +instret:3265 PC:0x1ffff0000000000000000000000002e68 instr:0x00000e93 iType:Alu [doCommitNormalInst [1]] 10111 +instret:3266 PC:0x1ffff0000000000000000000000002e6c instr:0x01a00193 iType:Alu [doCommitNormalInst [0]] 10112 + 101150 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080050eb4, toState: S, child: } + 101160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080050eb4, toState: S, child: } + 101160 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:3267 PC:0x1ffff0000000000000000000000002e70 instr:0x05d11263 iType:Br [doCommitNormalInst [0]] 10116 + 101170 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080050eb4, toState: S, child: } ; CRsMsg { addr: 'h0000000080050eb4, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3268 PC:0x1ffff0000000000000000000000002e74 instr:0x02000093 iType:Alu [doCommitNormalInst [0]] 10134 +instret:3269 PC:0x1ffff0000000000000000000000002e78 instr:0x0200813b iType:Alu [doCommitNormalInst [0]] 10137 +instret:3270 PC:0x1ffff0000000000000000000000002e7c instr:0x00000e93 iType:Alu [doCommitNormalInst [1]] 10137 +instret:3271 PC:0x1ffff0000000000000000000000002e80 instr:0x01b00193 iType:Alu [doCommitNormalInst [0]] 10138 +instret:3272 PC:0x1ffff0000000000000000000000002e84 instr:0x03d11863 iType:Br [doCommitNormalInst [0]] 10141 +instret:3273 PC:0x1ffff0000000000000000000000002e88 instr:0x020000bb iType:Alu [doCommitNormalInst [1]] 10141 +instret:3274 PC:0x1ffff0000000000000000000000002e8c instr:0x00000e93 iType:Alu [doCommitNormalInst [0]] 10142 +instret:3275 PC:0x1ffff0000000000000000000000002e90 instr:0x01c00193 iType:Alu [doCommitNormalInst [1]] 10142 +instret:3276 PC:0x1ffff0000000000000000000000002e94 instr:0x03d09063 iType:Br [doCommitNormalInst [0]] 10144 +instret:3277 PC:0x1ffff0000000000000000000000002e98 instr:0x02100093 iType:Alu [doCommitNormalInst [1]] 10144 +instret:3278 PC:0x1ffff0000000000000000000000002e9c instr:0x02200113 iType:Alu [doCommitNormalInst [0]] 10145 +instret:3279 PC:0x1ffff0000000000000000000000002ea0 instr:0x0220803b iType:Alu [doCommitNormalInst [1]] 10145 + 101460 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080050ec0, toState: S, child: } +instret:3280 PC:0x1ffff0000000000000000000000002ea4 instr:0x00000e93 iType:Alu [doCommitNormalInst [0]] 10146 +instret:3281 PC:0x1ffff0000000000000000000000002ea8 instr:0x01d00193 iType:Alu [doCommitNormalInst [1]] 10146 + 101470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080050ec0, toState: S, child: } + 101470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:3282 PC:0x1ffff0000000000000000000000002eac instr:0x01d01463 iType:Br [doCommitNormalInst [0]] 10147 +instret:3283 PC:0x1ffff0000000000000000000000002eb0 instr:0x00301a63 iType:Br [doCommitNormalInst [1]] 10147 + 101480 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080050ec0, toState: S, child: } ; CRsMsg { addr: 'h0000000080050ec0, toState: S, data: tagged Valid CLine { tag: , data: > }, child: } +instret:3284 PC:0x1ffff0000000000000000000000002ec4 instr:0x00100513 iType:Alu [doCommitNormalInst [0]] 10165 +instret:3285 PC:0x1ffff0000000000000000000000002ec8 instr:0x00000073 iType:Ecall [doCommitTrap] 10167 +instret:3286 PC:0x1ffff000000000000ffffffffffe000c8 instr:0x14011173 iType:Csr [doCommitSystemInst] 10182 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3287 PC:0x1ffff000000000000ffffffffffe000cc instr:0x00113423 iType:St [doCommitNormalInst [0]] 10194 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096f8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 101950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } +instret:3288 PC:0x1ffff000000000000ffffffffffe000d0 instr:0x00313c23 iType:St [doCommitNormalInst [0]] 10195 + 101960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 101960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 101960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 101960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff2c } + 101960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09700, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3289 PC:0x1ffff000000000000ffffffffffe000d4 instr:0x02413023 iType:St [doCommitNormalInst [0]] 10196 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09708, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 101970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } +instret:3290 PC:0x1ffff000000000000ffffffffffe000d8 instr:0x02513423 iType:St [doCommitNormalInst [0]] 10197 + 101980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 101980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 101980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 101980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800096e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff30 } + 101980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09710, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3291 PC:0x1ffff000000000000ffffffffffe000dc instr:0x02613823 iType:St [doCommitNormalInst [0]] 10198 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09718, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 101990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } +instret:3292 PC:0x1ffff000000000000ffffffffffe000e0 instr:0x02713c23 iType:St [doCommitNormalInst [0]] 10199 + 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800096f0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff34 } + 102000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3293 PC:0x1ffff000000000000ffffffffffe000e4 instr:0x04813023 iType:St [doCommitNormalInst [0]] 10200 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09728, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } +instret:3294 PC:0x1ffff000000000000ffffffffffe000e8 instr:0x04913423 iType:St [doCommitNormalInst [0]] 10201 + 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096f8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff38 } + 102020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09730, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3295 PC:0x1ffff000000000000ffffffffffe000ec instr:0x04a13823 iType:St [doCommitNormalInst [0]] 10202 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09738, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } +instret:3296 PC:0x1ffff000000000000ffffffffffe000f0 instr:0x04b13c23 iType:St [doCommitNormalInst [0]] 10203 + 102040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 102040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009700, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff3c } + 102040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09740, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3297 PC:0x1ffff000000000000ffffffffffe000f4 instr:0x06c13023 iType:St [doCommitNormalInst [0]] 10204 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09748, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } +instret:3298 PC:0x1ffff000000000000ffffffffffe000f8 instr:0x06d13423 iType:St [doCommitNormalInst [0]] 10205 + 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009708, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff00 } + 102060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09750, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3299 PC:0x1ffff000000000000ffffffffffe000fc instr:0x06e13823 iType:St [doCommitNormalInst [0]] 10206 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09758, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } +instret:3300 PC:0x1ffff000000000000ffffffffffe00100 instr:0x06f13c23 iType:St [doCommitNormalInst [0]] 10207 + 102080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 102080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009710, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff04 } + 102080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09760, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3301 PC:0x1ffff000000000000ffffffffffe00104 instr:0x09013023 iType:St [doCommitNormalInst [0]] 10208 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09768, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } +instret:3302 PC:0x1ffff000000000000ffffffffffe00108 instr:0x09113423 iType:St [doCommitNormalInst [0]] 10209 + 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009718, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff08 } + 102100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09770, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3303 PC:0x1ffff000000000000ffffffffffe0010c instr:0x09213823 iType:St [doCommitNormalInst [0]] 10210 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09778, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 102110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } +instret:3304 PC:0x1ffff000000000000ffffffffffe00110 instr:0x09313c23 iType:St [doCommitNormalInst [0]] 10211 + 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009720, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff0c } + 102120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09780, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3305 PC:0x1ffff000000000000ffffffffffe00114 instr:0x0b413023 iType:St [doCommitNormalInst [0]] 10212 + 102130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } +instret:3306 PC:0x1ffff000000000000ffffffffffe00118 instr:0x0b513423 iType:St [doCommitNormalInst [0]] 10213 + 102140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 102140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009728, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff10 } + 102140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09788, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3307 PC:0x1ffff000000000000ffffffffffe0011c instr:0x0b613823 iType:St [doCommitNormalInst [0]] 10214 + 102150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 102160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 102160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009730, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff14 } + 102160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09790, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3308 PC:0x1ffff000000000000ffffffffffe00120 instr:0x0b713c23 iType:St [doCommitNormalInst [0]] 10216 + 102170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 102180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 102180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009738, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff18 } + 102180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09798, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3309 PC:0x1ffff000000000000ffffffffffe00124 instr:0x0d813023 iType:St [doCommitNormalInst [0]] 10218 + 102190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 102200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 102200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009740, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hff1c } + 102200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3310 PC:0x1ffff000000000000ffffffffffe00128 instr:0x0d913423 iType:St [doCommitNormalInst [0]] 10220 + 102210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 102220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 102220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009748, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee0 } + 102220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3311 PC:0x1ffff000000000000ffffffffffe0012c instr:0x0da13823 iType:St [doCommitNormalInst [0]] 10222 + 102230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 102240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 102240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009750, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee4 } + 102240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3312 PC:0x1ffff000000000000ffffffffffe00130 instr:0x0db13c23 iType:St [doCommitNormalInst [0]] 10224 + 102250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009758, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfee8 } + 102260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3313 PC:0x1ffff000000000000ffffffffffe00134 instr:0x0fc13023 iType:St [doCommitNormalInst [0]] 10226 + 102270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 102280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 102280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080009760, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeec } + 102280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3314 PC:0x1ffff000000000000ffffffffffe00138 instr:0x0fd13423 iType:St [doCommitNormalInst [0]] 10228 + 102290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 102300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 102300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009768, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef0 } + 102300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3315 PC:0x1ffff000000000000ffffffffffe0013c instr:0x0fe13823 iType:St [doCommitNormalInst [0]] 10230 + 102310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 102320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 102320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009770, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef4 } + 102320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3316 PC:0x1ffff000000000000ffffffffffe00140 instr:0x0ff13c23 iType:St [doCommitNormalInst [0]] 10232 + 102330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 102340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 102340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009778, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfef8 } + 102340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 102360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 102360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009780, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfefc } + 102360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 102380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 102380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009788, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec0 } + 102380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 102400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 102400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009790, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec4 } + 102400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009798, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfec8 } + 102420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfecc } + 102440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 102460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 102460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed0 } + 102460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 102480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 102480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed4 } + 102480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 102500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 102500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800097b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfed8 } + 102500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 102520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 102520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800097c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfedc } + 102520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 102540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 102540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800097c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea0 } + 102540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3317 PC:0x1ffff000000000000ffffffffffe00144 instr:0x140112f3 iType:Csr [doCommitSystemInst] 10255 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3318 PC:0x1ffff000000000000ffffffffffe00148 instr:0x00513823 iType:St [doCommitNormalInst [0]] 10267 + 102680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfea8 } + 102690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3319 PC:0x1ffff000000000000ffffffffffe0014c instr:0x100022f3 iType:Csr [doCommitSystemInst] 10273 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097d8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3320 PC:0x1ffff000000000000ffffffffffe00150 instr:0x10513023 iType:St [doCommitNormalInst [0]] 10285 +instret:3321 PC:0x1ffff000000000000ffffffffffe00154 instr:0x141022f3 iType:Cap [doCommitNormalInst [1]] 10285 + 102860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } +instret:3322 PC:0x1ffff000000000000ffffffffffe00158 instr:0x10513423 iType:St [doCommitNormalInst [0]] 10286 + 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800097d0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb0 } + 102870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 102880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 102890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 102890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 102890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 102890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800097d8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfeb8 } + 102890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3323 PC:0x1ffff000000000000ffffffffffe0015c instr:0x143022f3 iType:Csr [doCommitSystemInst] 10292 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3324 PC:0x1ffff000000000000ffffffffffe00160 instr:0x10513823 iType:St [doCommitNormalInst [0]] 10304 + 103050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 103060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 103060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800097e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe80 } + 103060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3325 PC:0x1ffff000000000000ffffffffffe00164 instr:0x142022f3 iType:Csr [doCommitSystemInst] 10310 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe097e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3326 PC:0x1ffff000000000000ffffffffffe00168 instr:0x10513c23 iType:St [doCommitNormalInst [0]] 10322 +instret:3327 PC:0x1ffff000000000000ffffffffffe0016c instr:0x00010513 iType:Alu [doCommitNormalInst [1]] 10322 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 103230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } +instret:3328 PC:0x1ffff000000000000ffffffffffe00170 instr:0x4380206f iType:J [doCommitNormalInst [0]] 10323 + 103240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 103240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800097e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hfe88 } + 103240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096c8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096b0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3329 PC:0x1ffff000000000000ffffffffffe025a8 instr:0x11853583 iType:Ld [doCommitNormalInst [0]] 10326 +instret:3330 PC:0x1ffff000000000000ffffffffffe025ac instr:0xf9010113 iType:Alu [doCommitNormalInst [1]] 10326 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3331 PC:0x1ffff000000000000ffffffffffe025b0 instr:0x06813023 iType:St [doCommitNormalInst [0]] 10327 +instret:3332 PC:0x1ffff000000000000ffffffffffe025b4 instr:0x06113423 iType:St [doCommitNormalInst [1]] 10327 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe096a0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 103280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } +instret:3333 PC:0x1ffff000000000000ffffffffffe025b8 instr:0x04913c23 iType:St [doCommitNormalInst [0]] 10328 +instret:3334 PC:0x1ffff000000000000ffffffffffe025bc instr:0x05213823 iType:St [doCommitNormalInst [1]] 10328 + 103290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 103290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800096c0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda50 } + 103290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09698, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3335 PC:0x1ffff000000000000ffffffffffe025c0 instr:0x05313423 iType:St [doCommitNormalInst [0]] 10329 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09690, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 103300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } +instret:3336 PC:0x1ffff000000000000ffffffffffe025c4 instr:0x05413023 iType:St [doCommitNormalInst [0]] 10330 + 103310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 103310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800096c8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda54 } + 103310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09688, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3337 PC:0x1ffff000000000000ffffffffffe025c8 instr:0x03513c23 iType:St [doCommitNormalInst [0]] 10331 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09680, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 103320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } +instret:3338 PC:0x1ffff000000000000ffffffffffe025cc instr:0x03613823 iType:St [doCommitNormalInst [0]] 10332 + 103330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 103330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800096b8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda58 } + 103330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09678, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3339 PC:0x1ffff000000000000ffffffffffe025d0 instr:0x03713423 iType:St [doCommitNormalInst [0]] 10333 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09670, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 103340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } +instret:3340 PC:0x1ffff000000000000ffffffffffe025d4 instr:0x03813023 iType:St [doCommitNormalInst [0]] 10334 + 103350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 103350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800096b0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda5c } + 103350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09668, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:3341 PC:0x1ffff000000000000ffffffffffe025d8 instr:0x01913c23 iType:St [doCommitNormalInst [0]] 10335 + 103360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } +instret:3342 PC:0x1ffff000000000000ffffffffffe025dc instr:0x01a13823 iType:St [doCommitNormalInst [0]] 10336 + 103370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 103370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800096a8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda20 } + 103370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3343 PC:0x1ffff000000000000ffffffffffe025e0 instr:0x01b13423 iType:St [doCommitNormalInst [0]] 10337 +instret:3344 PC:0x1ffff000000000000ffffffffffe025e4 instr:0x00800793 iType:Alu [doCommitNormalInst [1]] 10337 + 103380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 103390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 103390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800096a0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda24 } + 103390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3345 PC:0x1ffff000000000000ffffffffffe025e8 instr:0x00050413 iType:Alu [doCommitNormalInst [0]] 10339 +instret:3346 PC:0x1ffff000000000000ffffffffffe025ec instr:0x12f58a63 iType:Br [doCommitNormalInst [1]] 10339 + 103400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 103410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 103410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080009698, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda28 } + 103410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 103430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 103430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080009690, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda2c } + 103430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 103450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 103450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080009688, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda30 } + 103450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080009680, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda34 } + 103470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 103490 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002720, toState: S, child: } + 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080009678, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda38 } + 103490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002720, toState: S, child: } + 103500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 103500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 103510 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002720, toState: S, child: } ; CRsMsg { addr: 'h0000000080002720, toState: S, data: tagged Invalid , child: } + 103510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 103510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080009670, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda3c } + 103510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 103530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 103530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080009668, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hda00 } + 103530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe09720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 103650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8c0 } + 103660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8c0 } + 103660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080009720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8c0 } + 103660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3347 PC:0x1ffff000000000000ffffffffffe02720 instr:0x05052903 iType:Ld [doCommitNormalInst [0]] 10369 +instret:3348 PC:0x1ffff000000000000ffffffffffe02724 instr:0x00001c37 iType:Alu [doCommitNormalInst [1]] 10369 +instret:3349 PC:0x1ffff000000000000ffffffffffe02728 instr:0x00006497 iType:Auipc [doCommitNormalInst [0]] 10370 +instret:3350 PC:0x1ffff000000000000ffffffffffe0272c instr:0xcc848493 iType:Alu [doCommitNormalInst [1]] 10370 +instret:3351 PC:0x1ffff000000000000ffffffffffe02730 instr:0x00002b97 iType:Auipc [doCommitNormalInst [0]] 10371 +instret:3352 PC:0x1ffff000000000000ffffffffffe02734 instr:0x8d0b8b93 iType:Alu [doCommitNormalInst [1]] 10371 + 103720 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002740, toState: S, child: } +instret:3353 PC:0x1ffff000000000000ffffffffffe02738 instr:0x00040b37 iType:Alu [doCommitNormalInst [0]] 10372 +instret:3354 PC:0x1ffff000000000000ffffffffffe0273c instr:0xffe00ab7 iType:Alu [doCommitNormalInst [1]] 10372 + 103730 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002740, toState: S, child: } + 103730 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 103740 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002740, toState: S, child: } ; CRsMsg { addr: 'h0000000080002740, toState: S, data: tagged Invalid , child: } +instret:3355 PC:0x1ffff000000000000ffffffffffe02740 instr:0x00006a17 iType:Auipc [doCommitNormalInst [0]] 10389 +instret:3356 PC:0x1ffff000000000000ffffffffffe02744 instr:0x0a0a0a13 iType:Alu [doCommitNormalInst [0]] 10390 +instret:3357 PC:0x1ffff000000000000ffffffffffe02748 instr:0x0003f9b7 iType:Alu [doCommitNormalInst [1]] 10390 +instret:3358 PC:0x1ffff000000000000ffffffffffe0274c instr:0x01c0006f iType:J [doCommitNormalInst [0]] 10391 +instret:3359 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 10393 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08400, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3360 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 10394 + 103950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080008400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:3361 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 10395 + 103960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 103960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080008400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 103960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 103960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080008400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 103960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 103980 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002780, toState: S, child: } + 103990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002780, toState: S, child: } + 103990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:3362 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 10399 + 104000 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002780, toState: S, child: } ; CRsMsg { addr: 'h0000000080002780, toState: S, data: tagged Invalid , child: } +instret:3363 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 10402 +instret:3364 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 10417 +instret:3365 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 10418 +instret:3366 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 10419 +instret:3367 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 10419 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08410, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3368 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 10420 + 104210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:3369 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 10421 + 104220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 104220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 104220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 104220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080008410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 104220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 104250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } +instret:3370 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 10425 + 104260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 104260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 104260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:3371 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 10427 +instret:3372 PC:0x1ffff000000000000ffffffffffe0277c instr:0x60078793 iType:Alu [doCommitNormalInst [1]] 10427 + 104280 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007010, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +instret:3373 PC:0x1ffff000000000000ffffffffffe02780 instr:0x00379793 iType:Alu [doCommitNormalInst [0]] 10428 +instret:3374 PC:0x1ffff000000000000ffffffffffe02784 instr:0x00fb87b3 iType:Alu [doCommitNormalInst [1]] 10428 + 104340 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } + 104350 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007010, toState: E, child: , data: tagged Invalid , id: 'h1 } + 104350 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } + 104350 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 104360 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } ; CRsMsg { addr: 'h00000000800027c0, toState: S, data: tagged Invalid , child: } + 104360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 104360 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 104360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080007010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 104360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3375 PC:0x1ffff000000000000ffffffffffe02788 instr:0x0007bc83 iType:Ld [doCommitNormalInst [0]] 10439 +instret:3376 PC:0x1ffff000000000000ffffffffffe0278c instr:0x040cf793 iType:Alu [doCommitNormalInst [0]] 10441 +instret:3377 PC:0x1ffff000000000000ffffffffffe02790 instr:0x0e078e63 iType:Br [doCommitNormalInst [0]] 10442 +instret:3378 PC:0x1ffff000000000000ffffffffffe02794 instr:0x100b2d73 iType:Csr [doCommitSystemInst] 10448 +instret:3379 PC:0x1ffff000000000000ffffffffffe02798 instr:0x015c0db3 iType:Alu [doCommitNormalInst [0]] 10462 +instret:3380 PC:0x1ffff000000000000ffffffffffe0279c instr:0x00001637 iType:Alu [doCommitNormalInst [1]] 10462 +instret:3381 PC:0x1ffff000000000000ffffffffffe027a0 instr:0x000d8593 iType:Alu [doCommitNormalInst [0]] 10463 +instret:3382 PC:0x1ffff000000000000ffffffffffe027a4 instr:0x000c0513 iType:Alu [doCommitNormalInst [1]] 10463 +instret:3383 PC:0x1ffff000000000000ffffffffffe027a8 instr:0x969ff0ef iType:J [doCommitNormalInst [0]] 10464 + 104670 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002110, toState: S, child: } + 104680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002110, toState: S, child: } + 104680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 104690 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002110, toState: S, child: } ; CRsMsg { addr: 'h0000000080002110, toState: S, data: tagged Invalid , child: } +instret:3384 PC:0x1ffff000000000000ffffffffffe02110 instr:0x00b567b3 iType:Alu [doCommitNormalInst [0]] 10484 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3385 PC:0x1ffff000000000000ffffffffffe02114 instr:0x0077f793 iType:Alu [doCommitNormalInst [0]] 10485 + 104860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdec8 } +instret:3386 PC:0x1ffff000000000000ffffffffffe02118 instr:0x04079463 iType:Br [doCommitNormalInst [0]] 10486 +instret:3387 PC:0x1ffff000000000000ffffffffffe0211c instr:0xff867813 iType:Alu [doCommitNormalInst [1]] 10486 + 104870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 104870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdec8 } + 104870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 104870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdec8 } + 104870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3388 PC:0x1ffff000000000000ffffffffffe02120 instr:0x01050833 iType:Alu [doCommitNormalInst [0]] 10487 +instret:3389 PC:0x1ffff000000000000ffffffffffe02124 instr:0x03057e63 iType:Br [doCommitNormalInst [0]] 10488 + 104900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdecc } +instret:3390 PC:0x1ffff000000000000ffffffffffe02128 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10490 + 104910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 104910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdecc } + 104910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 104910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050000, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdecc } + 104910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 104920 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002140, toState: S, child: } + 104930 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002140, toState: S, child: } + 104930 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 104940 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002140, toState: S, child: } ; CRsMsg { addr: 'h0000000080002140, toState: S, data: tagged Invalid , child: } +instret:3391 PC:0x1ffff000000000000ffffffffffe0212c instr:0x00053783 iType:Ld [doCommitNormalInst [0]] 10494 +instret:3392 PC:0x1ffff000000000000ffffffffffe02130 instr:0x02f71863 iType:Br [doCommitNormalInst [0]] 10496 +instret:3393 PC:0x1ffff000000000000ffffffffffe02134 instr:0x00050793 iType:Alu [doCommitNormalInst [1]] 10496 +instret:3394 PC:0x1ffff000000000000ffffffffffe02138 instr:0x0100006f iType:J [doCommitNormalInst [0]] 10497 +instret:3395 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 10511 +instret:3396 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [1]] 10511 +instret:3397 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [0]] 10513 + 105200 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } + 105210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } + 105210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 105220 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } ; CRsMsg { addr: 'h0000000080002180, toState: S, data: tagged Invalid , child: } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002008, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02008, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002008, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3398 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10543 +instret:3399 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10544 +instret:3400 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10546 +instret:3401 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10546 +instret:3402 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10547 +instret:3403 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10547 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02010, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080050010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080050010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080050010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080002010, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3404 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10555 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002018, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3405 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10556 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02018, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080050018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080050018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080050018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3406 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10558 +instret:3407 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10558 + 105590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080002018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002020, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3408 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10559 +instret:3409 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10559 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02020, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080050020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080050020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080050020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3410 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10561 + 105620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080002020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3411 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10562 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002028, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 105640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02028, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080050028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3412 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10564 +instret:3413 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10564 + 105650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080050028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080050028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3414 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10565 +instret:3415 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10565 + 105660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080002028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800500a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3416 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10566 +instret:3417 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10566 + 105670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800500a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800500a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002030, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105670 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3418 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10567 +instret:3419 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10567 + 105680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002060, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02030, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080050030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3420 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10568 +instret:3421 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10568 + 105690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080050030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080050030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3422 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10569 +instret:3423 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10569 + 105700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080002030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 105710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002038, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3424 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10571 +instret:3425 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10571 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02038, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080050038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3426 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10572 +instret:3427 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10572 + 105730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080050038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080050038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3428 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10573 +instret:3429 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10573 + 105740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080002038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002040, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3430 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10575 +instret:3431 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10575 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02040, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080050040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3432 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10576 +instret:3433 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10576 + 105770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080050040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080050040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3434 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10577 +instret:3435 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10577 + 105780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080002040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002048, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3436 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10579 +instret:3437 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10579 + 105800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800500c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02048, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080050048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3438 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10580 +instret:3439 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10580 + 105810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080050048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080050048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3440 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10581 +instret:3441 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10581 + 105820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080002048, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 105830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800020c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 105830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002050, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3442 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10583 +instret:3443 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10583 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02050, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080050050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3444 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10584 +instret:3445 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10584 + 105850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080050050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080050050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3446 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10585 +instret:3447 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10585 + 105860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080002050, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002058, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3448 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10587 +instret:3449 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10587 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02058, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080050058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3450 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10588 +instret:3451 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10588 + 105890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080050058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080050058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3452 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10589 +instret:3453 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10589 + 105900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080002058, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002060, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3454 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10591 +instret:3455 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10591 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02060, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080050060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3456 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10592 +instret:3457 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10592 + 105930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080050060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080050060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3458 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10593 +instret:3459 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10593 + 105940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002060, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002068, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3460 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10595 +instret:3461 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10595 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02068, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 105960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080050068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3462 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10596 +instret:3463 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10596 + 105970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080050068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080050068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 105970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 105970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3464 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10597 +instret:3465 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10597 + 105980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 105980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 105980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002068, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 105980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002070, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3466 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10599 +instret:3467 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10599 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02070, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080050070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3468 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10600 +instret:3469 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10600 + 106010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080050070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080050070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3470 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10601 +instret:3471 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10601 + 106020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080002070, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002078, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3472 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10603 +instret:3473 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10603 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02078, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080050078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3474 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10604 +instret:3475 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10604 + 106050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080050078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080050078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3476 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10605 +instret:3477 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10605 + 106060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080002078, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002080, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3478 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10607 +instret:3479 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10607 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02080, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3480 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10608 +instret:3481 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10608 + 106090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3482 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10609 +instret:3483 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10609 + 106100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080002080, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002088, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106110 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3484 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10611 +instret:3485 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10611 + 106120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02088, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080050088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3486 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10612 +instret:3487 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10612 + 106130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080050088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080050088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3488 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10613 +instret:3489 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10613 + 106140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080002088, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 106150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002100, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002090, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3490 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10615 +instret:3491 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10615 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02090, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080050090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3492 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10616 +instret:3493 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10616 + 106170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080050090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080050090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3494 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10617 +instret:3495 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10617 + 106180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002090, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002098, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3496 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10619 +instret:3497 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10619 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02098, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3498 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10620 +instret:3499 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10620 + 106210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3500 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10621 +instret:3501 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10621 + 106220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080002098, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3502 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10623 +instret:3503 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10623 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800500a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3504 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10624 +instret:3505 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10624 + 106250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800500a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800500a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3506 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10625 +instret:3507 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10625 + 106260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h00000000800020a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3508 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10627 +instret:3509 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10627 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800500a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3510 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10628 +instret:3511 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10628 + 106290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800500a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h00000000800500a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3512 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10629 +instret:3513 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10629 + 106300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800020a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3514 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10631 +instret:3515 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10631 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h00000000800500b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3516 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10632 +instret:3517 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10632 + 106330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h00000000800500b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h00000000800500b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3518 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10633 +instret:3519 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10633 + 106340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800020b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3520 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10635 +instret:3521 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10635 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800500b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3522 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10636 +instret:3523 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10636 + 106370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800500b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800500b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3524 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10637 +instret:3525 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10637 + 106380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800020b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3526 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10639 +instret:3527 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10639 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800500c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3528 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10640 +instret:3529 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10640 + 106410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800500c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800500c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3530 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10641 +instret:3531 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10641 + 106420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800020c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3532 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10643 +instret:3533 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10643 + 106440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800500c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3534 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10644 +instret:3535 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10644 + 106450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800500c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h00000000800500c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3536 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10645 +instret:3537 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10645 + 106460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800020c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 106470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002140, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3538 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10647 +instret:3539 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10647 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800500d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3540 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10648 +instret:3541 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10648 + 106490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800500d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h00000000800500d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3542 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10649 +instret:3543 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10649 + 106500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h00000000800020d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3544 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10651 +instret:3545 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10651 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800500d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3546 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10652 +instret:3547 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10652 + 106530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800500d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h00000000800500d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3548 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10653 +instret:3549 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10653 + 106540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800020d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3550 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10655 +instret:3551 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10655 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800500e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3552 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10656 +instret:3553 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10656 + 106570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800500e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800500e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3554 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10657 +instret:3555 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10657 + 106580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h00000000800020e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3556 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10659 +instret:3557 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10659 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800500e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3558 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10660 +instret:3559 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10660 + 106610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800500e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800500e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3560 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10661 +instret:3561 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10661 + 106620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800020e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3562 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10663 +instret:3563 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10663 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800500f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3564 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10664 +instret:3565 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10664 + 106650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800500f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800500f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3566 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10665 +instret:3567 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10665 + 106660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h00000000800020f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000020f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3568 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10667 +instret:3569 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10667 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe020f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h00000000800500f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3570 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10668 +instret:3571 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10668 + 106690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h00000000800500f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h00000000800500f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3572 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10669 +instret:3573 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10669 + 106700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800020f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002100, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3574 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10671 +instret:3575 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10671 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02100, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080050100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3576 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10672 +instret:3577 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10672 + 106730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080050100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080050100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3578 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10673 +instret:3579 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10673 + 106740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002108, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106750 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3580 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10675 +instret:3581 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10675 + 106760 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002100, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 106760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02108, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080050108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3582 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10676 +instret:3583 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10676 + 106770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080050108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080050108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3584 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10677 + 106780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 106780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 106790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002180, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 106790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002110, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02110, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002118, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02118, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080050118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080050118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080050118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002120, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02120, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 106880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 106890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h07, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 106890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h6 + 106920 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002100, toState: E, child: , data: tagged Invalid , id: 'h1 } + 106930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106930 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 106930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080002100, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 106940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 106940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002108, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 106950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 106950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080002110, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 106960 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } + 106960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 106960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +instret:3585 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10696 + 106970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 106970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 106970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 106970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 106980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } + 106980 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:3586 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10698 +instret:3587 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10698 + 106990 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } ; CRsMsg { addr: 'h000000008000213c, toState: S, data: tagged Invalid , child: } +instret:3588 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10699 +instret:3589 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10699 +instret:3590 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10700 +instret:3591 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10700 +instret:3592 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10701 +instret:3593 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10701 +instret:3594 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10702 +instret:3595 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10702 +instret:3596 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10703 +instret:3597 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10703 +instret:3598 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10704 +instret:3599 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10704 +instret:3600 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10705 +instret:3601 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10705 +instret:3602 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10706 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02118, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002120, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002118, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02120, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002128, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02128, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002130, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02130, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002138, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02138, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 107370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002118, toState: E, child: , data: tagged Invalid , id: 'h1 } + 107380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 107380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002118, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 107390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002120, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 107400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080002128, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 107410 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } + 107410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +instret:3603 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10741 + 107420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } + 107430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 107430 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002160, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3604 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10743 +instret:3605 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10743 + 107440 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } ; CRsMsg { addr: 'h000000008000213c, toState: S, data: tagged Invalid , child: } + 107440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002160, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002160, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3606 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10744 +instret:3607 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10744 + 107450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021a0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3608 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10745 +instret:3609 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10745 +instret:3610 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10746 +instret:3611 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10746 +instret:3612 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10747 +instret:3613 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10747 +instret:3614 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10748 +instret:3615 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10748 +instret:3616 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10749 +instret:3617 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10749 +instret:3618 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10750 +instret:3619 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10750 +instret:3620 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10751 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02130, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002138, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107660 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002130, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02138, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080050138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002140, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02140, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080050140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002148, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 107740 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002140, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 107740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02148, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080050148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080050148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080050148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002150, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02150, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 107780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080050150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080050150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080050150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 107790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 107820 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002130, toState: E, child: , data: tagged Invalid , id: 'h1 } + 107830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107830 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 107830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080002130, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 107840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080002138, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107860 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } +instret:3621 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10786 + 107870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } + 107870 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 107880 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h000000008000213c, toState: S, child: } ; CRsMsg { addr: 'h000000008000213c, toState: S, data: tagged Invalid , child: } +instret:3622 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10788 +instret:3623 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10788 +instret:3624 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10789 +instret:3625 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10789 + 107900 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002140, toState: E, child: , data: tagged Invalid , id: 'h1 } +instret:3626 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10790 +instret:3627 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10790 + 107910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107910 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 107910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080002140, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:3628 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10791 +instret:3629 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10791 + 107920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080002148, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:3630 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10792 +instret:3631 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10792 + 107930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 107930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080002150, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 107930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3632 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10793 + 107940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3633 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10794 + 107950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002188, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 107950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 107960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 107960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 107960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 107960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3634 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10796 +instret:3635 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10796 +instret:3636 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10797 +instret:3637 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10797 +instret:3638 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10798 +instret:3639 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10798 +instret:3640 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10799 +instret:3641 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10799 +instret:3642 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10800 +instret:3643 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10800 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002158, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3644 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10801 +instret:3645 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10801 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02158, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3646 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10802 +instret:3647 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10802 + 108030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080050158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3648 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10803 +instret:3649 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10803 + 108040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080002158, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3650 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10806 + 108070 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } +instret:3651 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10807 + 108080 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 108080 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 108090 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } ; CRsMsg { addr: 'h0000000080002148, toState: S, data: tagged Invalid , child: } +instret:3652 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10809 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002160, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3653 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 10824 +instret:3654 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [1]] 10824 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02160, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080050160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3655 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [0]] 10825 + 108260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080050160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080050160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002168, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002160, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02168, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080050168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3656 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10829 + 108300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080050168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080050168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002170, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02170, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080050170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 108440 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 108450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002160, toState: E, child: , data: tagged Invalid , id: 'h1 } + 108450 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002180, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 108450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 108460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080002160, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 108470 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 108470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 108470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080002168, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 108480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 108480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 108490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 108490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3657 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10849 + 108500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 108500 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 108510 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } ; CRsMsg { addr: 'h0000000080002148, toState: S, data: tagged Invalid , child: } + 108510 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800021b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3658 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10851 +instret:3659 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10851 + 108520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800021b8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 108520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3660 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10852 +instret:3661 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10852 + 108530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:3662 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10853 +instret:3663 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10853 +instret:3664 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10854 +instret:3665 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10854 +instret:3666 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10855 +instret:3667 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10855 +instret:3668 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10856 + 108610 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002180, toState: E, child: , data: tagged Invalid , id: 'h1 } + 108620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108620 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 108620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 108650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02170, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108710 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002170, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080050178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002188, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 108790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800501c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02188, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108810 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 108820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050200, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 108820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002190, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02190, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 108830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 108840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 108850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108870 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002170, toState: E, child: , data: tagged Invalid , id: 'h1 } + 108880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108880 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 108880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080002170, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 108890 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 108890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 108890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 108890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 108890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 108900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 108900 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 108910 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } ; CRsMsg { addr: 'h0000000080002148, toState: S, data: tagged Invalid , child: } +instret:3669 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10891 +instret:3670 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10893 +instret:3671 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10893 +instret:3672 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10894 +instret:3673 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10894 +instret:3674 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10895 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02178, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109100 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002178, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02180, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002180, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002188, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02188, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002188, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002190, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800501c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800501c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800501c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02190, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002190, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109200 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002198, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800021c8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02198, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002198, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109240 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002208, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109260 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002178, toState: E, child: , data: tagged Invalid , id: 'h1 } + 109270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 109270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002178, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109280 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 109290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } + 109290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 109300 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002148, toState: S, child: } ; CRsMsg { addr: 'h0000000080002148, toState: S, data: tagged Invalid , child: } +instret:3675 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10930 +instret:3676 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10932 +instret:3677 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10932 +instret:3678 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10933 +instret:3679 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10933 +instret:3680 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10934 +instret:3681 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10934 +instret:3682 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10935 +instret:3683 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10935 +instret:3684 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10936 +instret:3685 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10936 +instret:3686 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10937 +instret:3687 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10937 +instret:3688 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10938 +instret:3689 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10938 +instret:3690 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10939 +instret:3691 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10939 +instret:3692 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10940 +instret:3693 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10940 +instret:3694 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10941 +instret:3695 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10941 +instret:3696 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10942 +instret:3697 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10942 +instret:3698 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10943 +instret:3699 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10943 +instret:3700 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10944 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3701 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [0]] 10945 +instret:3702 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [1]] 10945 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800501a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3703 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [0]] 10946 + 109470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800501a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800501a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h00000000800021a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800501a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3704 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10950 + 109510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800501a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800501a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3705 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 10951 + 109520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h00000000800021a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3706 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10953 +instret:3707 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10953 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800501b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3708 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10954 +instret:3709 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10954 + 109550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800501b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800501b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3710 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10955 +instret:3711 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10955 + 109560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800021b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3712 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10957 +instret:3713 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10957 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800501b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3714 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10958 +instret:3715 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10958 + 109590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800501b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h00000000800501b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3716 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10959 +instret:3717 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10959 + 109600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h00000000800021b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3718 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10961 +instret:3719 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10961 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800501c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3720 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10962 +instret:3721 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10962 + 109630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800501c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800501c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3722 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10963 +instret:3723 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10963 + 109640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800021c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800021f8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002238, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3724 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10965 +instret:3725 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10965 + 109660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002238, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002238, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800501c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3726 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10966 +instret:3727 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10966 + 109670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800501c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800501c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3728 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10967 +instret:3729 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10967 + 109680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h00000000800021c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109680 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 109690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3730 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10969 +instret:3731 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10969 + 109700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002240, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800501d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3732 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10970 +instret:3733 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10970 + 109710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800501d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800501d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3734 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10971 +instret:3735 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10971 + 109720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800021d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3736 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10973 +instret:3737 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10973 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800501d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3738 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10974 +instret:3739 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10974 + 109750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800501d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800501d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3740 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10975 +instret:3741 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10975 + 109760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800021d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3742 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10977 +instret:3743 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10977 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800501e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3744 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10978 +instret:3745 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10978 + 109790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800501e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800501e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3746 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10979 +instret:3747 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10979 + 109800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h00000000800021e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3748 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10981 +instret:3749 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10981 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3750 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10982 +instret:3751 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10982 + 109830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800501e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3752 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10983 +instret:3753 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10983 + 109840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800021e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3754 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10985 +instret:3755 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10985 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800501f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3756 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10986 +instret:3757 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10986 + 109870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800501f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800501f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3758 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10987 +instret:3759 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10987 + 109880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h00000000800021f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000021f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3760 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10989 +instret:3761 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10989 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe021f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800501f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3762 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10990 +instret:3763 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10990 + 109910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800501f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h00000000800501f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3764 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10991 +instret:3765 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10991 + 109920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800021f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002200, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3766 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10993 +instret:3767 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10993 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02200, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3768 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10994 +instret:3769 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10994 + 109950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3770 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10995 +instret:3771 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10995 + 109960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002200, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 109960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002208, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3772 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 10997 +instret:3773 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 10997 + 109980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 109980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02208, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 109980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3774 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 10998 +instret:3775 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 10998 + 109990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 109990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 109990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 109990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 109990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3776 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 10999 +instret:3777 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 10999 + 110000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002208, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 110010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002280, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002210, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3778 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11001 +instret:3779 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11001 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02210, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3780 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11002 +instret:3781 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11002 + 110030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3782 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11003 +instret:3783 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11003 + 110040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002210, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002218, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3784 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11005 +instret:3785 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11005 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02218, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3786 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11006 +instret:3787 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11006 + 110070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3788 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11007 +instret:3789 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11007 + 110080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002218, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002220, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3790 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11009 +instret:3791 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11009 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02220, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3792 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11010 +instret:3793 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11010 + 110110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3794 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11011 +instret:3795 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11011 + 110120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080002220, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002228, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3796 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11013 +instret:3797 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11013 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02228, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3798 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11014 +instret:3799 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11014 + 110150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3800 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11015 +instret:3801 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11015 + 110160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002228, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002230, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3802 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11017 +instret:3803 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11017 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02230, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3804 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11018 +instret:3805 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11018 + 110190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3806 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11019 +instret:3807 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11019 + 110200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002230, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002238, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3808 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11021 +instret:3809 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11021 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02238, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3810 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11022 +instret:3811 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11022 + 110230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3812 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11023 +instret:3813 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11023 + 110240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002238, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002240, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3814 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11025 +instret:3815 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11025 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02240, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080050240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3816 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11026 +instret:3817 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11026 + 110270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080050240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h16, addr: 'h0000000080050240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3818 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11027 +instret:3819 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11027 + 110280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h17, addr: 'h0000000080002240, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002248, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3820 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11029 +instret:3821 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11029 + 110300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02248, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3822 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11030 +instret:3823 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11030 + 110310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3824 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11031 +instret:3825 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11031 + 110320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002248, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 110330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800022c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002250, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3826 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11033 +instret:3827 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11033 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02250, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3828 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11034 +instret:3829 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11034 + 110350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3830 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11035 +instret:3831 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11035 + 110360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002250, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002258, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3832 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11037 +instret:3833 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11037 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02258, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3834 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11038 +instret:3835 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11038 + 110390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3836 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11039 +instret:3837 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11039 + 110400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002258, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002260, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3838 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11041 +instret:3839 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11041 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02260, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3840 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11042 +instret:3841 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11042 + 110430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3842 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11043 +instret:3843 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11043 + 110440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002260, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002268, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3844 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11045 +instret:3845 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11045 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02268, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3846 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11046 +instret:3847 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11046 + 110470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3848 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11047 +instret:3849 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11047 + 110480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002268, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002270, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3850 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11049 +instret:3851 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11049 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02270, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3852 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11050 +instret:3853 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11050 + 110510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3854 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11051 +instret:3855 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11051 + 110520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002270, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002278, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3856 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11053 +instret:3857 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11053 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02278, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3858 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11054 +instret:3859 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11054 + 110550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3860 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11055 +instret:3861 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11055 + 110560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002278, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002280, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3862 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11057 +instret:3863 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11057 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02280, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3864 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11058 +instret:3865 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11058 + 110590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3866 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11059 +instret:3867 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11059 + 110600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002280, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002288, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3868 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11061 +instret:3869 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11061 + 110620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02288, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3870 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11062 +instret:3871 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11062 + 110630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3872 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11063 +instret:3873 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11063 + 110640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002288, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 110650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002300, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002290, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3874 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11065 +instret:3875 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11065 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02290, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3876 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11066 +instret:3877 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11066 + 110670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3878 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11067 +instret:3879 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11067 + 110680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002290, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002298, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3880 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11069 +instret:3881 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11069 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02298, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3882 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11070 +instret:3883 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11070 + 110710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3884 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11071 +instret:3885 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11071 + 110720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002298, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3886 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11073 +instret:3887 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11073 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800502a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3888 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11074 +instret:3889 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11074 + 110750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800502a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800502a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3890 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11075 +instret:3891 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11075 + 110760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h00000000800022a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3892 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11077 +instret:3893 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11077 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3894 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11078 +instret:3895 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11078 + 110790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h00000000800502a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3896 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11079 +instret:3897 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11079 + 110800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800022a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3898 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11081 +instret:3899 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11081 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800502b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3900 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11082 +instret:3901 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11082 + 110830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800502b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h00000000800502b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3902 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11083 +instret:3903 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11083 + 110840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h00000000800022b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3904 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11085 +instret:3905 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11085 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800502b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3906 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11086 +instret:3907 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11086 + 110870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800502b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800502b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3908 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11087 +instret:3909 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11087 + 110880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h00000000800022b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3910 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11089 +instret:3911 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11089 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800502c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3912 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11090 +instret:3913 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11090 + 110910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800502c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h00000000800502c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3914 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11091 +instret:3915 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11091 + 110920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800022c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3916 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11093 +instret:3917 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11093 + 110940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800502c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3918 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11094 +instret:3919 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11094 + 110950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800502c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800502c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3920 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11095 +instret:3921 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11095 + 110960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800022c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 110960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 110970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002340, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 110970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3922 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11097 +instret:3923 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11097 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 110980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3924 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11098 +instret:3925 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11098 + 110990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 110990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 110990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800502d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 110990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 110990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3926 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11099 +instret:3927 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11099 + 111000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h00000000800022d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3928 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11101 +instret:3929 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11101 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800502d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3930 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11102 +instret:3931 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11102 + 111030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800502d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800502d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3932 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11103 +instret:3933 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11103 + 111040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800022d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3934 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11105 +instret:3935 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11105 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h00000000800502e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3936 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11106 +instret:3937 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11106 + 111070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h00000000800502e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h00000000800502e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3938 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11107 +instret:3939 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11107 + 111080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h00000000800022e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3940 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11109 +instret:3941 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11109 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800502e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3942 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11110 +instret:3943 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11110 + 111110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800502e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800502e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3944 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11111 +instret:3945 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11111 + 111120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h00000000800022e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3946 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11113 +instret:3947 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11113 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800502f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3948 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11114 +instret:3949 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11114 + 111150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800502f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800502f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3950 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11115 +instret:3951 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11115 + 111160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h00000000800022f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000022f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3952 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11117 +instret:3953 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11117 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe022f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800502f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3954 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11118 +instret:3955 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11118 + 111190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800502f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800502f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3956 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11119 +instret:3957 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11119 + 111200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800022f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002300, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3958 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11121 +instret:3959 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11121 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02300, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3960 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11122 +instret:3961 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11122 + 111230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3962 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11123 +instret:3963 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11123 + 111240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002308, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3964 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11125 +instret:3965 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11125 + 111260 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002300, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 111260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02308, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3966 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11126 +instret:3967 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11126 + 111270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3968 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11127 + 111280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 + 111280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 111290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002380, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002310, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02310, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002318, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02318, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002320, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02320, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h3 + 111420 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002300, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002328, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 111430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002300, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02328, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002308, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 111450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002310, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 111460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002318, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002330, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3969 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11146 + 111470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002320, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02330, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3970 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11148 +instret:3971 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11148 + 111490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002328, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3972 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11149 +instret:3973 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11149 + 111500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3974 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11150 +instret:3975 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11150 + 111510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002330, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002338, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3976 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11151 +instret:3977 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11151 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02338, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3978 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11152 +instret:3979 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11152 + 111530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3980 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11153 +instret:3981 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11153 + 111540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002338, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002340, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3982 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11154 +instret:3983 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11154 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02340, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3984 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11155 +instret:3985 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11155 + 111560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0e, addr: 'h0000000080050340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3986 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11156 +instret:3987 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11156 + 111570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:3988 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11157 +instret:3989 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11157 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002348, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3990 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11158 +instret:3991 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11158 + 111590 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002340, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 111590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800503c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02348, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:3992 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11159 +instret:3993 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11159 + 111600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:3994 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11160 +instret:3995 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11160 + 111610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 111610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:3996 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11161 +instret:3997 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11161 + 111620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h00000000800023c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002350, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:3998 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11162 +instret:3999 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11162 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02350, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4000 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11163 +instret:4001 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11163 + 111640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4002 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11164 +instret:4003 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11164 + 111650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 +instret:4004 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11165 +instret:4005 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11165 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002358, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4006 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11166 +instret:4007 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11166 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02358, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4008 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11167 +instret:4009 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11167 + 111680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4010 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11168 +instret:4011 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11168 + 111690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 +instret:4012 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11169 +instret:4013 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11169 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002360, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4014 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11170 +instret:4015 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11170 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02360, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4016 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11171 + 111720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 + 111750 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002340, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002368, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 111760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002340, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02368, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002348, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 111780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002350, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 111790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002358, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002370, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4017 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11179 + 111800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 111800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002360, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02370, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h0000000080050368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4018 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11181 +instret:4019 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11181 + 111820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002368, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4020 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11182 +instret:4021 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11182 + 111830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002378, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4022 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11183 +instret:4023 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11183 + 111840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002370, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02378, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4024 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11184 +instret:4025 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11184 + 111850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4026 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11185 +instret:4027 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11185 + 111860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002378, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4028 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11186 +instret:4029 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11186 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002380, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4030 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11187 +instret:4031 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11187 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02380, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4032 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11188 +instret:4033 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11188 + 111890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4034 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11189 +instret:4035 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11189 + 111900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002380, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4036 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11190 +instret:4037 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11190 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002388, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4038 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11191 +instret:4039 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11191 + 111920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02388, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4040 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11192 +instret:4041 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11192 + 111930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4042 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11193 +instret:4043 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11193 + 111940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002388, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4044 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11194 +instret:4045 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11194 + 111950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002400, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 111950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002390, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4046 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11195 +instret:4047 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11195 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02390, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 111960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4048 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11196 +instret:4049 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11196 + 111970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 111970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 111970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4050 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11197 +instret:4051 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11197 + 111980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 111980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 111980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002390, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 111980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4052 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11198 +instret:4053 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11198 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002398, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4054 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11199 +instret:4055 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11199 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02398, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4056 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11200 +instret:4057 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11200 + 112010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4058 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11201 +instret:4059 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11201 + 112020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002398, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4060 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11202 +instret:4061 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11202 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4062 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11203 +instret:4063 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11203 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800503a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4064 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11204 +instret:4065 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11204 + 112050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800503a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h00000000800503a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4066 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11205 +instret:4067 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11205 + 112060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800023a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4068 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11206 +instret:4069 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11206 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4070 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11207 +instret:4071 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11207 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800503a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4072 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11208 +instret:4073 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11208 + 112090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800503a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800503a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4074 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11209 +instret:4075 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11209 + 112100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800023a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4076 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11210 +instret:4077 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11210 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4078 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11211 +instret:4079 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11211 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800503b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4080 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11212 +instret:4081 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11212 + 112130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800503b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800503b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4082 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11213 +instret:4083 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11213 + 112140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800023b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4084 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11214 +instret:4085 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11214 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4086 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11215 +instret:4087 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11215 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800503b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4088 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11216 +instret:4089 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11216 + 112170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800503b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800503b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4090 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11217 +instret:4091 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11217 + 112180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800023b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4092 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11218 +instret:4093 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11218 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4094 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11219 +instret:4095 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11219 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800503c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4096 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11220 +instret:4097 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11220 + 112210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800503c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h00000000800503c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4098 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11221 +instret:4099 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11221 + 112220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4100 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11222 +instret:4101 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11222 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4102 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11223 +instret:4103 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11223 + 112240 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800023c0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 112240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4104 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11224 +instret:4105 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11224 + 112250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h00000000800503c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4106 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11225 +instret:4107 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11225 + 112260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 112260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4108 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11226 +instret:4109 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11226 + 112270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002440, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4110 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11227 +instret:4111 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11227 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800503d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4112 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11228 + 112290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800503d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800503d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800503d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800503d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h00000000800503d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800503e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800503e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800503e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 + 112400 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800023c0, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112410 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 112410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800023c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800503e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800023c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 112430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h00000000800023d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 112440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800023d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4113 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11244 + 112450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800023e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800503e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h00000000800503e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4114 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11246 +instret:4115 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11246 + 112470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800023e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800503f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4116 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11247 +instret:4117 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11247 + 112480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800503f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800503f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000023f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4118 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11248 +instret:4119 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11248 + 112490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800023f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe023f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800503f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4120 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11249 +instret:4121 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11249 + 112500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800503f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800503f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4122 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11250 +instret:4123 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11250 + 112510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h00000000800023f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4124 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11251 +instret:4125 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11251 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002400, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4126 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11252 +instret:4127 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11252 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02400, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4128 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11253 +instret:4129 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11253 + 112540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4130 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11254 +instret:4131 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11254 + 112550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4132 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11255 +instret:4133 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11255 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002408, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112560 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4134 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11256 +instret:4135 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11256 + 112570 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002400, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 112570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02408, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4136 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11257 +instret:4137 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11257 + 112580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4138 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11258 +instret:4139 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11258 + 112590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 112590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4140 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11259 +instret:4141 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11259 + 112600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002480, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002410, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4142 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11260 +instret:4143 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11260 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02410, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4144 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11261 +instret:4145 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11261 + 112620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4146 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11262 +instret:4147 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11262 + 112630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h7 +instret:4148 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11263 +instret:4149 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11263 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002418, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4150 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11264 +instret:4151 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11264 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02418, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4152 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11265 +instret:4153 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11265 + 112660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4154 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11266 +instret:4155 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11266 + 112670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 +instret:4156 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11267 +instret:4157 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11267 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002420, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4158 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11268 +instret:4159 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11268 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02420, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4160 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11269 + 112700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h5 + 112730 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002400, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002428, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112740 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 112740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002400, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02428, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002408, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 112760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002410, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 112770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002418, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002430, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4161 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11277 + 112780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 112780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02430, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4162 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11279 +instret:4163 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11279 + 112800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002428, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4164 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11280 +instret:4165 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11280 + 112810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002438, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4166 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11281 +instret:4167 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11281 + 112820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02438, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4168 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11282 +instret:4169 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11282 + 112830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4170 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11283 +instret:4171 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11283 + 112840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002438, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4172 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11284 +instret:4173 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11284 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002440, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4174 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11285 +instret:4175 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11285 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02440, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4176 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11286 +instret:4177 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11286 + 112870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4178 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11287 +instret:4179 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11287 + 112880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4180 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11288 +instret:4181 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11288 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002448, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4182 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11289 +instret:4183 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11289 + 112900 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002440, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 112900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800504c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02448, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4184 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11290 +instret:4185 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11290 + 112910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4186 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11291 +instret:4187 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11291 + 112920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 112920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4188 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11292 +instret:4189 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11292 + 112930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800024c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 112930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002450, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4190 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11293 +instret:4191 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11293 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02450, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4192 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11294 +instret:4193 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11294 + 112950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4194 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11295 +instret:4195 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11295 + 112960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 112960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 +instret:4196 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11296 +instret:4197 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11296 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002458, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4198 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11297 +instret:4199 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11297 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02458, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 112980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4200 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11298 +instret:4201 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11298 + 112990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 112990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 112990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 112990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 112990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4202 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11299 +instret:4203 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11299 + 113000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +instret:4204 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11300 +instret:4205 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11300 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002460, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4206 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11301 +instret:4207 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11301 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02460, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4208 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11302 + 113030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 113060 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002440, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002468, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113070 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 113070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02468, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 113080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002448, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 113090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 113090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 113100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 113100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002458, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002470, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4209 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11310 + 113110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 113110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02470, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4210 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11312 +instret:4211 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11312 + 113130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002468, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4212 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11313 +instret:4213 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11313 + 113140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002478, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4214 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11314 +instret:4215 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11314 + 113150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02478, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4216 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11315 +instret:4217 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11315 + 113160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4218 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11316 +instret:4219 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11316 + 113170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002478, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4220 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11317 +instret:4221 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11317 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002480, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4222 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11318 +instret:4223 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11318 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02480, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4224 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11319 +instret:4225 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11319 + 113200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4226 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11320 +instret:4227 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11320 + 113210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4228 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11321 +instret:4229 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11321 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002488, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113220 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4230 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11322 +instret:4231 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11322 + 113230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02488, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4232 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11323 +instret:4233 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11323 + 113240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4234 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11324 +instret:4235 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11324 + 113250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002488, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4236 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11325 +instret:4237 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11325 + 113260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002500, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002490, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4238 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11326 +instret:4239 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11326 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02490, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4240 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11327 +instret:4241 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11327 + 113280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4242 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11328 +instret:4243 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11328 + 113290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4244 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11329 +instret:4245 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11329 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002498, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4246 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11330 +instret:4247 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11330 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02498, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4248 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11331 +instret:4249 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11331 + 113320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4250 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11332 +instret:4251 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11332 + 113330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002498, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4252 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11333 +instret:4253 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11333 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4254 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11334 +instret:4255 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11334 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800504a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4256 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11335 +instret:4257 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11335 + 113360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800504a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800504a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4258 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11336 +instret:4259 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11336 + 113370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h00000000800024a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4260 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11337 +instret:4261 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11337 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4262 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11338 +instret:4263 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11338 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800504a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4264 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11339 +instret:4265 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11339 + 113400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800504a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h00000000800504a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4266 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11340 +instret:4267 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11340 + 113410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h00000000800024a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4268 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11341 +instret:4269 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11341 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4270 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11342 +instret:4271 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11342 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800504b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4272 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11343 +instret:4273 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11343 + 113440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800504b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800504b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4274 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11344 +instret:4275 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11344 + 113450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800024b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4276 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11345 +instret:4277 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11345 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4278 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11346 +instret:4279 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11346 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800504b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4280 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11347 +instret:4281 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11347 + 113480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800504b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800504b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4282 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11348 +instret:4283 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11348 + 113490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h00000000800024b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4284 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11349 +instret:4285 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11349 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4286 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11350 +instret:4287 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11350 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800504c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4288 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11351 +instret:4289 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11351 + 113520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800504c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800504c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4290 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11352 +instret:4291 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11352 + 113530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h00000000800024c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4292 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11353 +instret:4293 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11353 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113540 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4294 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11354 +instret:4295 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11354 + 113550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800504c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4296 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11355 +instret:4297 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11355 + 113560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800504c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h00000000800504c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4298 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11356 +instret:4299 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11356 + 113570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h00000000800024c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113570 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4300 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11357 +instret:4301 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11357 + 113580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002540, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4302 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11358 +instret:4303 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11358 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800504d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4304 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11359 +instret:4305 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11359 + 113600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800504d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800504d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4306 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11360 +instret:4307 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11360 + 113610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800024d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4308 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11361 +instret:4309 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11361 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4310 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11362 +instret:4311 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11362 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800504d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4312 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11363 +instret:4313 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11363 + 113640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800504d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800504d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4314 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11364 +instret:4315 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11364 + 113650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h00000000800024d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4316 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11365 +instret:4317 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11365 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4318 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11366 +instret:4319 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11366 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800504e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4320 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11367 +instret:4321 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11367 + 113680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800504e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h00000000800504e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4322 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11368 +instret:4323 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11368 + 113690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800024e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4324 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11370 +instret:4325 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11370 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4326 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11371 +instret:4327 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11371 + 113720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800504e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4328 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11372 +instret:4329 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11372 + 113730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h00000000800024e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4330 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11374 +instret:4331 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11374 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800504f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4332 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11375 +instret:4333 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11375 + 113760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800504f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800504f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4334 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11376 +instret:4335 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11376 + 113770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800024f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000024f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4336 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11378 +instret:4337 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11378 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe024f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800504f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4338 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11379 +instret:4339 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11379 + 113800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800504f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800504f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4340 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11380 +instret:4341 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11380 + 113810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h00000000800024f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002500, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4342 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11382 +instret:4343 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11382 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02500, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4344 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11383 +instret:4345 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11383 + 113840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4346 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11384 +instret:4347 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11384 + 113850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002508, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4348 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11386 +instret:4349 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11386 + 113870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02508, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4350 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11387 +instret:4351 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11387 + 113880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4352 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11388 +instret:4353 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11388 + 113890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002508, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113890 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 113900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 113900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002510, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4354 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11390 +instret:4355 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11390 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02510, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4356 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11391 +instret:4357 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11391 + 113920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4358 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11392 +instret:4359 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11392 + 113930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002518, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4360 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11394 +instret:4361 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11394 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02518, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4362 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11395 +instret:4363 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11395 + 113960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 113960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 113960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4364 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11396 +instret:4365 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11396 + 113970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 113970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 113970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002518, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 113970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002520, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4366 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11398 +instret:4367 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11398 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02520, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 113990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4368 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11399 +instret:4369 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11399 + 114000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4370 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11400 +instret:4371 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11400 + 114010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002528, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4372 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11402 +instret:4373 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11402 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02528, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4374 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11403 +instret:4375 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11403 + 114040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4376 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11404 +instret:4377 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11404 + 114050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002528, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002530, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4378 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11406 +instret:4379 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11406 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02530, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4380 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11407 +instret:4381 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11407 + 114080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4382 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11408 +instret:4383 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11408 + 114090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002538, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4384 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11410 +instret:4385 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11410 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02538, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4386 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11411 +instret:4387 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11411 + 114120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4388 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11412 +instret:4389 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11412 + 114130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002538, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002540, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4390 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11414 +instret:4391 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11414 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02540, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4392 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11415 +instret:4393 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11415 + 114160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4394 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11416 +instret:4395 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11416 + 114170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h17, addr: 'h0000000080002540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002548, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114180 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4396 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11418 +instret:4397 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11418 + 114190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800505c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02548, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4398 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11419 +instret:4399 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11419 + 114200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4400 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11420 +instret:4401 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11420 + 114210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002548, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 114220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800025c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002550, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4402 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11422 +instret:4403 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11422 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02550, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4404 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11423 +instret:4405 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11423 + 114240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4406 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11424 +instret:4407 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11424 + 114250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002558, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4408 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11426 +instret:4409 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11426 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02558, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4410 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11427 +instret:4411 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11427 + 114280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4412 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11428 +instret:4413 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11428 + 114290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002558, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002560, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4414 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11430 +instret:4415 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11430 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02560, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4416 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11431 +instret:4417 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11431 + 114320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4418 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11432 +instret:4419 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11432 + 114330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002568, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4420 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11434 +instret:4421 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11434 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02568, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4422 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11435 +instret:4423 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11435 + 114360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4424 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11436 +instret:4425 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11436 + 114370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002568, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002570, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4426 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11438 +instret:4427 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11438 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02570, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4428 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11439 +instret:4429 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11439 + 114400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4430 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11440 +instret:4431 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11440 + 114410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002578, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4432 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11442 +instret:4433 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11442 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02578, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4434 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11443 +instret:4435 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11443 + 114440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4436 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11444 +instret:4437 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11444 + 114450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002578, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002580, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4438 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11446 +instret:4439 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11446 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02580, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4440 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11447 +instret:4441 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11447 + 114480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4442 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11448 +instret:4443 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11448 + 114490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002588, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114500 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4444 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11450 +instret:4445 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11450 + 114510 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002580, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 114510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02588, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4446 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11451 +instret:4447 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11451 + 114520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4448 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11452 + 114530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 114530 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 114540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002590, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02590, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002598, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02598, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800505a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800505a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h00000000800505a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h7 + 114670 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002580, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114680 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 114680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 114690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002588, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 114700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 114700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 114710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 114710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002598, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4449 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11471 + 114720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 114720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800025a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800505a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4450 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11473 +instret:4451 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11473 + 114740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h00000000800025a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800505b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4452 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11474 +instret:4453 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11474 + 114750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800505b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800505b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4454 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11475 +instret:4455 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11475 + 114760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800025b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800505b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4456 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11476 +instret:4457 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11476 + 114770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800505b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h00000000800505b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4458 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11477 +instret:4459 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11477 + 114780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h00000000800025b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4460 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11478 +instret:4461 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11478 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4462 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11479 +instret:4463 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11479 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800505c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4464 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11480 +instret:4465 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11480 + 114810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800505c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800505c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4466 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11481 +instret:4467 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11481 + 114820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4468 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11482 +instret:4469 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11482 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4470 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11483 +instret:4471 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11483 + 114840 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800025c0, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 114840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h00000000800505c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4472 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11484 +instret:4473 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11484 + 114850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h00000000800505c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h00000000800505c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4474 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11485 +instret:4475 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11485 + 114860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 114860 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4476 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11486 +instret:4477 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11486 + 114870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 114870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4478 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11487 +instret:4479 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11487 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800505d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4480 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11488 +instret:4481 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11488 + 114890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800505d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800505d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4482 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11489 +instret:4483 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11489 + 114900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 +instret:4484 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11490 +instret:4485 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11490 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4486 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11491 +instret:4487 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11491 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800505d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4488 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11492 +instret:4489 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11492 + 114930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800505d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800505d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4490 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11493 +instret:4491 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11493 + 114940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +instret:4492 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11494 +instret:4493 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11494 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4494 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11495 +instret:4495 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11495 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 114960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800505e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4496 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11496 + 114970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800505e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 114970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800505e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 114970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 114970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 114980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 114980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 + 115000 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800025c0, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115010 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 115010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800025c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800505e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800025c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 115030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h00000000800025d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 115040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h00000000800025d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4497 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11504 + 115050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800025e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800505e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h00000000800505e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4498 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11506 +instret:4499 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11506 + 115070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800025e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800505f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4500 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11507 +instret:4501 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11507 + 115080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800505f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800505f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000025f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4502 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11508 +instret:4503 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11508 + 115090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h00000000800025f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe025f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800505f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4504 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11509 +instret:4505 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11509 + 115100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800505f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800505f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4506 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11510 +instret:4507 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11510 + 115110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800025f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4508 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11511 +instret:4509 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11511 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002600, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4510 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11512 +instret:4511 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11512 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02600, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4512 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11513 +instret:4513 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11513 + 115140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4514 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11514 +instret:4515 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11514 + 115150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4516 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11515 +instret:4517 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11515 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002608, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115160 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4518 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11516 +instret:4519 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11516 + 115170 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002600, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 115170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02608, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4520 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11517 +instret:4521 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11517 + 115180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4522 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11518 +instret:4523 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11518 + 115190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 115190 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4524 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11519 +instret:4525 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11519 + 115200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002610, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4526 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11520 +instret:4527 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11520 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02610, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4528 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11521 +instret:4529 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11521 + 115220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4530 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11522 +instret:4531 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11522 + 115230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 +instret:4532 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11523 +instret:4533 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11523 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002618, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4534 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11524 +instret:4535 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11524 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02618, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4536 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11525 +instret:4537 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11525 + 115260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4538 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11526 +instret:4539 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11526 + 115270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 +instret:4540 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11527 +instret:4541 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11527 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002620, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4542 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11528 +instret:4543 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11528 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02620, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4544 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11529 + 115300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 + 115330 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002600, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002628, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115340 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 115340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02628, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002608, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 115360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 115370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002618, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002630, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4545 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11537 + 115380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02630, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4546 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11539 +instret:4547 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11539 + 115400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002628, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4548 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11540 +instret:4549 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11540 + 115410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002638, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4550 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11541 +instret:4551 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11541 + 115420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02638, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4552 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11542 +instret:4553 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11542 + 115430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4554 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11543 +instret:4555 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11543 + 115440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002638, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4556 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11544 +instret:4557 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11544 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002640, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4558 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11545 +instret:4559 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11545 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02640, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4560 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11546 +instret:4561 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11546 + 115470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4562 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11547 +instret:4563 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11547 + 115480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4564 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11548 +instret:4565 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11548 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002648, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4566 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11549 +instret:4567 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11549 + 115500 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002640, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 115500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02648, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4568 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11550 +instret:4569 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11550 + 115510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080050648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4570 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11551 +instret:4571 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11551 + 115520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 115520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4572 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11552 +instret:4573 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11552 + 115530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800026c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002650, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4574 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11553 +instret:4575 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11553 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02650, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4576 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11554 +instret:4577 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11554 + 115550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4578 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11555 +instret:4579 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11555 + 115560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 +instret:4580 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11556 +instret:4581 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11556 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002658, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4582 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11557 +instret:4583 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11557 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02658, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4584 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11558 +instret:4585 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11558 + 115590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4586 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11559 +instret:4587 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11559 + 115600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 +instret:4588 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11560 +instret:4589 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11560 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002660, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4590 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11561 +instret:4591 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11561 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02660, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4592 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11562 + 115630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 + 115660 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002640, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002668, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115670 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 115670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02668, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002648, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 115690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 115700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002658, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4593 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11570 + 115710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 115710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4594 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11572 +instret:4595 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11572 + 115730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002668, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4596 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11573 +instret:4597 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11573 + 115740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002678, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4598 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11574 +instret:4599 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11574 + 115750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02678, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4600 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11575 +instret:4601 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11575 + 115760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4602 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11576 +instret:4603 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11576 + 115770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002678, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4604 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11577 +instret:4605 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11577 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4606 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11578 +instret:4607 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11578 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4608 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11579 +instret:4609 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11579 + 115800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4610 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11580 +instret:4611 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11580 + 115810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4612 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11581 +instret:4613 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11581 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002688, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4614 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11582 +instret:4615 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11582 + 115830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02688, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4616 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11583 +instret:4617 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11583 + 115840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4618 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11584 +instret:4619 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11584 + 115850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002688, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115850 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4620 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11585 +instret:4621 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11585 + 115860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 115860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4622 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11586 +instret:4623 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11586 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4624 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11587 +instret:4625 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11587 + 115880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4626 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11588 +instret:4627 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11588 + 115890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4628 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11589 +instret:4629 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11589 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002698, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4630 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11590 +instret:4631 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11590 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02698, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4632 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11591 +instret:4633 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11591 + 115920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4634 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11592 +instret:4635 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11592 + 115930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002698, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4636 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11593 +instret:4637 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11593 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4638 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11594 +instret:4639 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11594 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800506a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4640 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11595 +instret:4641 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11595 + 115960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800506a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h00000000800506a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 115960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 115960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4642 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11596 +instret:4643 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11596 + 115970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 115970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 115970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800026a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 115970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4644 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11597 +instret:4645 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11597 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4646 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11598 +instret:4647 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11598 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 115990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800506a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4648 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11599 +instret:4649 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11599 + 116000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800506a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800506a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4650 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11600 +instret:4651 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11600 + 116010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800026a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4652 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11601 +instret:4653 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11601 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4654 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11602 +instret:4655 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11602 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h00000000800506b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4656 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11603 +instret:4657 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11603 + 116040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h00000000800506b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h00000000800506b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4658 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11604 +instret:4659 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11604 + 116050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800026b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4660 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11605 +instret:4661 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11605 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4662 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11606 +instret:4663 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11606 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800506b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4664 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11607 +instret:4665 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11607 + 116080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800506b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800506b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4666 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11608 +instret:4667 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11608 + 116090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800026b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4668 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11609 +instret:4669 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11609 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4670 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11610 +instret:4671 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11610 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800506c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4672 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11611 +instret:4673 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11611 + 116120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800506c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800506c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4674 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11612 +instret:4675 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11612 + 116130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800026c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4676 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11613 +instret:4677 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11613 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4678 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11614 +instret:4679 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11614 + 116150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4680 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11615 +instret:4681 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11615 + 116160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800506c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4682 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11616 +instret:4683 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11616 + 116170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h00000000800026c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116170 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4684 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11617 +instret:4685 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11617 + 116180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080002740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4686 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11618 +instret:4687 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11618 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800506d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4688 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11619 +instret:4689 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11619 + 116200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800506d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h00000000800506d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4690 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11620 +instret:4691 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11620 + 116210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800026d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4692 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11621 +instret:4693 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11621 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4694 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11622 +instret:4695 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11622 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800506d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4696 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11623 +instret:4697 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11623 + 116240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800506d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800506d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4698 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11624 +instret:4699 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11624 + 116250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800026d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4700 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11625 +instret:4701 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11625 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4702 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11626 +instret:4703 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11626 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800506e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4704 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11627 +instret:4705 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11627 + 116280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800506e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h00000000800506e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4706 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11628 +instret:4707 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11628 + 116290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800026e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4708 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11630 +instret:4709 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11630 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800506e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4710 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11631 +instret:4711 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11631 + 116320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800506e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h00000000800506e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4712 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11632 +instret:4713 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11632 + 116330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h00000000800026e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4714 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11634 +instret:4715 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11634 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4716 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11635 +instret:4717 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11635 + 116360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800506f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4718 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11636 +instret:4719 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11636 + 116370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800026f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000026f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4720 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11638 +instret:4721 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11638 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe026f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800506f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4722 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11639 +instret:4723 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11639 + 116400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800506f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h00000000800506f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4724 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11640 +instret:4725 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11640 + 116410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800026f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4726 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11642 +instret:4727 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11642 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4728 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11643 +instret:4729 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11643 + 116440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4730 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11644 +instret:4731 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11644 + 116450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002708, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116460 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4732 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11646 +instret:4733 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11646 + 116470 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002700, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 116470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02708, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4734 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11647 +instret:4735 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11647 + 116480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4736 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11648 + 116490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 116490 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 116500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002718, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02718, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h7 + 116630 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002700, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002728, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116640 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 116640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02728, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002708, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 116660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 116670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080002718, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4737 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11667 + 116680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4738 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11669 +instret:4739 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11669 + 116700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002728, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4740 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11670 +instret:4741 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11670 + 116710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4742 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11671 +instret:4743 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11671 + 116720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002738, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4744 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11672 +instret:4745 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11672 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02738, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4746 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11673 +instret:4747 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11673 + 116740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4748 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11674 +instret:4749 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11674 + 116750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h0000000080002738, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4750 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11675 +instret:4751 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11675 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4752 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11676 +instret:4753 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11676 + 116770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4754 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11677 +instret:4755 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11677 + 116780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4756 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11678 +instret:4757 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11678 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002748, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116790 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4758 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11679 +instret:4759 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11679 + 116800 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002740, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 116800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800507c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02748, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080050748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4760 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11680 +instret:4761 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11680 + 116810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080050748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h0000000080050748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4762 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11681 +instret:4763 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11681 + 116820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 116820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4764 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11682 +instret:4765 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11682 + 116830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h00000000800027c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 116830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4766 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11683 +instret:4767 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11683 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4768 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11684 +instret:4769 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11684 + 116850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4770 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11685 +instret:4771 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11685 + 116860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 +instret:4772 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11686 +instret:4773 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11686 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002758, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4774 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11687 +instret:4775 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11687 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02758, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4776 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11688 +instret:4777 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11688 + 116890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4778 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11689 +instret:4779 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11689 + 116900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 +instret:4780 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11690 +instret:4781 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11690 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4782 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11691 +instret:4783 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11691 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4784 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11692 + 116930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 116930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 116930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h0 + 116960 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002740, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002768, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116970 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 116970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02768, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 116970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 116980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002748, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 116990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 116990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 116990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 116990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 117000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002758, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4785 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11700 + 117010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4786 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11702 +instret:4787 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11702 + 117030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002768, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4788 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11703 +instret:4789 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11703 + 117040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002778, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4790 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11704 +instret:4791 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11704 + 117050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02778, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4792 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11705 +instret:4793 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11705 + 117060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4794 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11706 +instret:4795 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11706 + 117070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h0000000080002778, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4796 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11707 +instret:4797 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11707 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4798 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11708 +instret:4799 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11708 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4800 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11709 +instret:4801 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11709 + 117100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4802 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11710 +instret:4803 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11710 + 117110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4804 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11711 +instret:4805 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11711 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002788, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117120 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4806 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11712 +instret:4807 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11712 + 117130 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h0, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080002780, fromState: S, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 117130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02788, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4808 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11713 +instret:4809 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11713 + 117140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4810 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11714 +instret:4811 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11714 + 117150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 + 117150 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4812 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11715 +instret:4813 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11715 + 117160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002800, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4814 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11716 +instret:4815 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11716 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4816 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11717 +instret:4817 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11717 + 117180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4818 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11718 +instret:4819 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11718 + 117190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h6 +instret:4820 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11719 +instret:4821 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11719 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002798, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4822 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11720 +instret:4823 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11720 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02798, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4824 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11721 +instret:4825 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11721 + 117220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4826 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11722 +instret:4827 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11722 + 117230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 +instret:4828 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11723 +instret:4829 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11723 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4830 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11724 +instret:4831 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11724 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800507a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4832 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11725 + 117260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800507a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800507a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h5 + 117290 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080002780, toState: E, child: , data: tagged Invalid , id: 'h0 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117300 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 117300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800507a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002788, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 117320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 117330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002798, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4833 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11733 + 117340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h00000000800027a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800507a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800507a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4834 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11735 +instret:4835 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11735 + 117360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h00000000800027a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800507b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4836 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11736 +instret:4837 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11736 + 117370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800507b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800507b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4838 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11737 +instret:4839 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11737 + 117380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h00000000800027b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h00000000800507b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4840 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11738 +instret:4841 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11738 + 117390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h00000000800507b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h00000000800507b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4842 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11739 +instret:4843 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11739 + 117400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800027b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4844 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11740 +instret:4845 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11740 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4846 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11741 +instret:4847 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11741 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800507c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4848 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11742 +instret:4849 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11742 + 117430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800507c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800507c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4850 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11743 +instret:4851 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11743 + 117440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:4852 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11744 +instret:4853 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11744 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4854 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11745 +instret:4855 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11745 + 117460 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800027c0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } + 117460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800507c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4856 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11746 +instret:4857 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11746 + 117470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800507c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h00000000800507c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4858 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11747 +instret:4859 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11747 + 117480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 + 117480 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4860 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11748 +instret:4861 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11748 + 117490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002840, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4862 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11749 +instret:4863 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11749 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800507d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4864 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11750 +instret:4865 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11750 + 117510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800507d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800507d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4866 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11751 +instret:4867 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11751 + 117520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h7 +instret:4868 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11752 +instret:4869 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11752 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4870 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11753 +instret:4871 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11753 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800507d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4872 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11754 +instret:4873 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11754 + 117550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800507d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h00000000800507d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4874 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11755 +instret:4875 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11755 + 117560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 +instret:4876 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11756 +instret:4877 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11756 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4878 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11757 +instret:4879 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11757 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800507e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4880 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11758 + 117590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800507e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h00000000800507e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: S, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h4 + 117620 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800027c0, toState: E, child: , data: tagged Invalid , id: 'h1 } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117630 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 117630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h00000000800027c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h00000000800027c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 117650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h00000000800027d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 117660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h00000000800027d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4881 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 11766 + 117670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 117670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800027e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h00, addr: 'h00000000800507e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4882 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11768 +instret:4883 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11768 + 117690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h00000000800027e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800507f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4884 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11769 +instret:4885 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11769 + 117700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800507f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800507f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000027f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4886 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11770 +instret:4887 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11770 + 117710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800027f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe027f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800507f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4888 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11771 +instret:4889 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11771 + 117720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800507f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800507f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4890 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11772 +instret:4891 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11772 + 117730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800027f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4892 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11773 +instret:4893 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11773 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002800, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4894 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11774 +instret:4895 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11774 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02800, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080050800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4896 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11775 +instret:4897 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11775 + 117760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080050800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h0000000080050800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4898 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11776 +instret:4899 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11776 + 117770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h0000000080002800, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4900 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11777 +instret:4901 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11777 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002808, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117780 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4902 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11778 +instret:4903 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11778 + 117790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02808, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4904 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11779 +instret:4905 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11779 + 117800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4906 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11780 +instret:4907 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11780 + 117810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002808, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117810 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4908 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11781 +instret:4909 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11781 + 117820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002880, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 117820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002810, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4910 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11782 +instret:4911 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11782 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02810, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4912 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11783 +instret:4913 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11783 + 117840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4914 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11784 +instret:4915 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11784 + 117850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002810, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4916 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11785 +instret:4917 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11785 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002818, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4918 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11786 +instret:4919 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11786 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02818, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4920 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11787 +instret:4921 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11787 + 117880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4922 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11788 +instret:4923 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11788 + 117890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002818, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4924 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11789 +instret:4925 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11789 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002820, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4926 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11790 +instret:4927 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11790 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02820, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4928 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11791 +instret:4929 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11791 + 117920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4930 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11792 +instret:4931 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11792 + 117930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002820, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4932 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11793 +instret:4933 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11793 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002828, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4934 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11794 +instret:4935 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11794 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02828, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4936 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11795 +instret:4937 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11795 + 117960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 117960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 117960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4938 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11796 +instret:4939 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11796 + 117970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 117970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 117970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002828, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 117970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4940 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11797 +instret:4941 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11797 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002830, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4942 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11798 +instret:4943 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11798 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02830, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 117990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4944 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11799 +instret:4945 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11799 + 118000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4946 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11800 +instret:4947 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11800 + 118010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002830, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4948 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11801 +instret:4949 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11801 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002838, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4950 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11802 +instret:4951 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11802 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02838, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4952 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11803 +instret:4953 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11803 + 118040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4954 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11804 +instret:4955 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11804 + 118050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002838, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4956 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11805 +instret:4957 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11805 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002840, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4958 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11806 +instret:4959 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11806 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02840, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4960 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11807 +instret:4961 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11807 + 118080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4962 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11808 +instret:4963 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11808 + 118090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002840, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4964 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11809 +instret:4965 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11809 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002848, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118100 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4966 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11810 +instret:4967 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11810 + 118110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02848, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4968 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11811 +instret:4969 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11811 + 118120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4970 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11812 +instret:4971 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11812 + 118130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002848, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:4972 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11813 +instret:4973 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11813 + 118140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800028c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002850, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4974 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11814 +instret:4975 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11814 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02850, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4976 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11815 +instret:4977 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11815 + 118160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4978 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11816 +instret:4979 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11816 + 118170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002850, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4980 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11817 +instret:4981 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11817 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002858, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4982 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11818 +instret:4983 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11818 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02858, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4984 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11819 +instret:4985 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11819 + 118200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4986 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11820 +instret:4987 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11820 + 118210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002858, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:4988 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11821 +instret:4989 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11821 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002860, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4990 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11822 +instret:4991 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11822 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02860, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4992 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11823 +instret:4993 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11823 + 118240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:4994 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11824 +instret:4995 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11824 + 118250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002860, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002868, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:4996 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11826 +instret:4997 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11826 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02868, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:4998 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11827 +instret:4999 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11827 + 118280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h08, addr: 'h0000000080050868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5000 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11828 +instret:5001 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11828 + 118290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002868, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002870, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5002 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11830 +instret:5003 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11830 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02870, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5004 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11831 +instret:5005 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11831 + 118320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5006 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11832 +instret:5007 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11832 + 118330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002870, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002878, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5008 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11834 +instret:5009 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11834 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02878, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5010 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11835 +instret:5011 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11835 + 118360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5012 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11836 +instret:5013 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11836 + 118370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002878, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002880, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5014 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11838 +instret:5015 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11838 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02880, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5016 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11839 +instret:5017 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11839 + 118400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5018 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11840 +instret:5019 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11840 + 118410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002880, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002888, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118420 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5020 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11842 +instret:5021 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11842 + 118430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02888, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5022 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11843 +instret:5023 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11843 + 118440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h10, addr: 'h0000000080050888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5024 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11844 +instret:5025 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11844 + 118450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002888, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 118460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002900, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002890, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5026 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11846 +instret:5027 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11846 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02890, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5028 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11847 +instret:5029 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11847 + 118480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5030 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11848 +instret:5031 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11848 + 118490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002890, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002898, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5032 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11850 +instret:5033 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11850 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02898, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5034 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11851 +instret:5035 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11851 + 118520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5036 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11852 +instret:5037 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11852 + 118530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002898, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5038 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11854 +instret:5039 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11854 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800508a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5040 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11855 +instret:5041 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11855 + 118560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800508a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800508a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5042 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11856 +instret:5043 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11856 + 118570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800028a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5044 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11858 +instret:5045 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11858 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5046 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11859 +instret:5047 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11859 + 118600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800508a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5048 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11860 +instret:5049 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11860 + 118610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800028a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5050 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11862 +instret:5051 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11862 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800508b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5052 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11863 +instret:5053 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11863 + 118640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800508b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h00000000800508b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5054 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11864 +instret:5055 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11864 + 118650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h00000000800028b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5056 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11866 +instret:5057 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11866 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800508b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5058 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11867 +instret:5059 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11867 + 118680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800508b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h00000000800508b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5060 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11868 +instret:5061 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11868 + 118690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h00000000800028b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5062 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11870 +instret:5063 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11870 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800508c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5064 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11871 +instret:5065 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11871 + 118720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800508c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h00000000800508c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5066 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11872 +instret:5067 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11872 + 118730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800028c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118740 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5068 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11874 +instret:5069 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11874 + 118750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h00000000800508c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5070 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11875 +instret:5071 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11875 + 118760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h00000000800508c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h00000000800508c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5072 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11876 +instret:5073 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11876 + 118770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800028c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 118780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002940, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 118780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5074 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11878 +instret:5075 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11878 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5076 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11879 +instret:5077 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11879 + 118800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800508d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5078 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11880 +instret:5079 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11880 + 118810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800028d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5080 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11882 +instret:5081 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11882 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800508d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5082 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11883 +instret:5083 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11883 + 118840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800508d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800508d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5084 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11884 +instret:5085 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11884 + 118850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800028d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5086 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11886 +instret:5087 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11886 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800508e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5088 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11887 +instret:5089 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11887 + 118880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800508e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h00000000800508e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5090 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11888 +instret:5091 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11888 + 118890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h00000000800028e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5092 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11890 +instret:5093 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11890 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800508e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5094 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11891 +instret:5095 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11891 + 118920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800508e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h00000000800508e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5096 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11892 +instret:5097 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11892 + 118930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h00000000800028e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5098 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11894 +instret:5099 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11894 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800508f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5100 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11895 +instret:5101 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11895 + 118960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800508f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h00000000800508f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 118960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 118960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5102 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11896 +instret:5103 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11896 + 118970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 118970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 118970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h00000000800028f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 118970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000028f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5104 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11898 +instret:5105 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11898 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe028f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 118990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800508f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5106 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11899 +instret:5107 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11899 + 119000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800508f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h00000000800508f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5108 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11900 +instret:5109 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11900 + 119010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h15, addr: 'h00000000800028f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002900, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5110 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11902 +instret:5111 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11902 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02900, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5112 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11903 +instret:5113 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11903 + 119040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h16, addr: 'h0000000080050900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5114 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11904 +instret:5115 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11904 + 119050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h0000000080002900, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002908, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119060 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5116 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11906 +instret:5117 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11906 + 119070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02908, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5118 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11907 +instret:5119 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11907 + 119080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080050908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5120 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11908 +instret:5121 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11908 + 119090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002908, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119090 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 119100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002980, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002910, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5122 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11910 +instret:5123 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11910 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02910, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5124 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11911 +instret:5125 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11911 + 119120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5126 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11912 +instret:5127 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11912 + 119130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002910, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002918, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5128 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11914 +instret:5129 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11914 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02918, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5130 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11915 +instret:5131 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11915 + 119160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5132 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11916 +instret:5133 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11916 + 119170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002918, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002920, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5134 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11918 +instret:5135 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11918 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02920, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5136 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11919 +instret:5137 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11919 + 119200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5138 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11920 +instret:5139 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11920 + 119210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002920, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002928, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5140 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11922 +instret:5141 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11922 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02928, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5142 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11923 +instret:5143 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11923 + 119240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5144 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11924 +instret:5145 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11924 + 119250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002928, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002930, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5146 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11926 +instret:5147 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11926 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02930, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5148 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11927 +instret:5149 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11927 + 119280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5150 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11928 +instret:5151 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11928 + 119290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002930, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002938, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5152 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11930 +instret:5153 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11930 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02938, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5154 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11931 +instret:5155 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11931 + 119320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5156 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11932 +instret:5157 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11932 + 119330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002938, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002940, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5158 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11934 +instret:5159 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11934 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02940, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5160 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11935 +instret:5161 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11935 + 119360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5162 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11936 +instret:5163 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11936 + 119370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002940, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002948, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5164 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11938 +instret:5165 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11938 + 119390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02948, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5166 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11939 +instret:5167 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11939 + 119400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5168 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11940 +instret:5169 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11940 + 119410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002948, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119410 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 119420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800029c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002950, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5170 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11942 +instret:5171 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11942 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02950, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5172 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11943 +instret:5173 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11943 + 119440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5174 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11944 +instret:5175 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11944 + 119450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002950, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002958, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5176 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11946 +instret:5177 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11946 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02958, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5178 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11947 +instret:5179 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11947 + 119480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5180 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11948 +instret:5181 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11948 + 119490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002958, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002960, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5182 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11950 +instret:5183 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11950 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02960, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5184 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11951 +instret:5185 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11951 + 119520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5186 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11952 +instret:5187 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11952 + 119530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002960, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002968, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5188 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11954 +instret:5189 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11954 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02968, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5190 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11955 +instret:5191 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11955 + 119560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080050968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5192 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11956 +instret:5193 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11956 + 119570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002968, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002970, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5194 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11958 +instret:5195 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11958 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02970, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5196 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11959 +instret:5197 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11959 + 119600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5198 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11960 +instret:5199 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11960 + 119610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002970, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002978, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5200 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11962 +instret:5201 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11962 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02978, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5202 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11963 +instret:5203 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11963 + 119640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5204 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11964 +instret:5205 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11964 + 119650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080002978, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002980, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5206 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11966 +instret:5207 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11966 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02980, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5208 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11967 +instret:5209 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11967 + 119680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080050980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5210 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11968 +instret:5211 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11968 + 119690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h07, addr: 'h0000000080002980, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002988, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119700 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5212 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11970 +instret:5213 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11970 + 119710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02988, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5214 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11971 +instret:5215 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11971 + 119720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h08, addr: 'h0000000080050988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5216 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11972 +instret:5217 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11972 + 119730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002988, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119730 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 119740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002a00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 119740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002990, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5218 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11974 +instret:5219 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11974 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02990, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5220 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11975 +instret:5221 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11975 + 119760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5222 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11976 +instret:5223 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11976 + 119770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002990, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002998, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5224 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11978 +instret:5225 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11978 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02998, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5226 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11979 +instret:5227 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11979 + 119800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5228 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11980 +instret:5229 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11980 + 119810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002998, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5230 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11982 +instret:5231 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11982 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800509a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5232 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11983 +instret:5233 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11983 + 119840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800509a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h00000000800509a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5234 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11984 +instret:5235 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11984 + 119850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h00000000800029a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5236 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11986 +instret:5237 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11986 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029a8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h00000000800509a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5238 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11987 +instret:5239 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11987 + 119880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h00000000800509a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h00000000800509a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5240 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11988 +instret:5241 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11988 + 119890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800029a8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5242 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11990 +instret:5243 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11990 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800509b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5244 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11991 +instret:5245 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11991 + 119920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800509b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h00000000800509b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5246 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11992 +instret:5247 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11992 + 119930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h00000000800029b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5248 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11994 +instret:5249 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11994 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029b8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800509b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5250 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11995 +instret:5251 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11995 + 119960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800509b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800509b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 119960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 119960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5252 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 11996 +instret:5253 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 11996 + 119970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 119970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 119970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h00000000800029b8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 119970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5254 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 11998 +instret:5255 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 11998 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 119990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800509c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5256 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 11999 +instret:5257 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 11999 + 120000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800509c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h00000000800509c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5258 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12000 +instret:5259 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12000 + 120010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h00000000800029c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120020 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5260 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12002 +instret:5261 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12002 + 120030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029c8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5262 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12003 +instret:5263 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12003 + 120040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800509c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5264 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12004 +instret:5265 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12004 + 120050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h00000000800029c8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120050 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 120060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002a40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5266 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12006 +instret:5267 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12006 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800509d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5268 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12007 +instret:5269 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12007 + 120080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800509d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h00000000800509d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5270 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12008 +instret:5271 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12008 + 120090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h00000000800029d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5272 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12010 +instret:5273 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12010 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029d8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800509d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5274 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12011 +instret:5275 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12011 + 120120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800509d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h00000000800509d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5276 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12012 +instret:5277 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12012 + 120130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h05, addr: 'h00000000800029d8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5278 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12014 +instret:5279 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12014 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800509e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5280 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12015 +instret:5281 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12015 + 120160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800509e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h06, addr: 'h00000000800509e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5282 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12016 +instret:5283 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12016 + 120170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h07, addr: 'h00000000800029e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5284 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12018 +instret:5285 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12018 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029e8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800509e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5286 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12019 +instret:5287 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12019 + 120200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800509e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h08, addr: 'h00000000800509e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5288 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12020 +instret:5289 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12020 + 120210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h00000000800029e8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5290 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12022 +instret:5291 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12022 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5292 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12023 +instret:5293 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12023 + 120240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800509f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5294 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12024 +instret:5295 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12024 + 120250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800029f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h00000000000029f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5296 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12026 +instret:5297 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12026 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe029f8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800509f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5298 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12027 +instret:5299 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12027 + 120280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800509f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h00000000800509f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5300 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12028 +instret:5301 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12028 + 120290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h00000000800029f8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5302 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12030 +instret:5303 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12030 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080050a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5304 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12031 +instret:5305 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12031 + 120320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080050a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080050a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5306 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12032 +instret:5307 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12032 + 120330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0f, addr: 'h0000000080002a00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120340 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5308 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12034 +instret:5309 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12034 + 120350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5310 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12035 +instret:5311 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12035 + 120360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h10, addr: 'h0000000080050a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5312 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12036 +instret:5313 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12036 + 120370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002a08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120370 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 120380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080002a80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5314 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12038 +instret:5315 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12038 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5316 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12039 +instret:5317 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12039 + 120400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5318 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12040 +instret:5319 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12040 + 120410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002a10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5320 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12042 +instret:5321 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12042 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5322 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12043 +instret:5323 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12043 + 120440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5324 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12044 +instret:5325 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12044 + 120450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002a18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5326 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12046 +instret:5327 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12046 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5328 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12047 +instret:5329 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12047 + 120480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5330 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12048 +instret:5331 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12048 + 120490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002a20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5332 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12050 +instret:5333 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12050 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5334 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12051 +instret:5335 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12051 + 120520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5336 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12052 +instret:5337 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12052 + 120530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002a28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5338 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12054 +instret:5339 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12054 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5340 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12055 +instret:5341 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12055 + 120560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5342 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12056 +instret:5343 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12056 + 120570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002a30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5344 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12058 +instret:5345 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12058 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5346 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12059 +instret:5347 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12059 + 120600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5348 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12060 +instret:5349 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12060 + 120610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002a38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5350 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12062 +instret:5351 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12062 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5352 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12063 +instret:5353 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12063 + 120640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5354 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12064 +instret:5355 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12064 + 120650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002a40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5356 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12066 +instret:5357 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12066 + 120670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5358 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12067 +instret:5359 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12067 + 120680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5360 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12068 +instret:5361 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12068 + 120690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002a48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 120700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ac0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5362 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12070 +instret:5363 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12070 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5364 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12071 +instret:5365 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12071 + 120720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5366 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12072 +instret:5367 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12072 + 120730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002a50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5368 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12074 +instret:5369 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12074 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5370 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12075 +instret:5371 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12075 + 120760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5372 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12076 +instret:5373 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12076 + 120770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0d, addr: 'h0000000080002a58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5374 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12078 +instret:5375 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12078 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5376 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12079 +instret:5377 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12079 + 120800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0e, addr: 'h0000000080050a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5378 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12080 +instret:5379 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12080 + 120810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0f, addr: 'h0000000080002a60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5380 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12082 +instret:5381 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12082 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5382 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12083 +instret:5383 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12083 + 120840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5384 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12084 +instret:5385 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12084 + 120850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002a68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5386 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12086 +instret:5387 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12086 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5388 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12087 +instret:5389 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12087 + 120880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5390 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12088 +instret:5391 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12088 + 120890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002a70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5392 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12090 +instret:5393 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12090 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5394 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12091 +instret:5395 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12091 + 120920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5396 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12092 +instret:5397 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12092 + 120930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h15, addr: 'h0000000080002a78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5398 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12094 +instret:5399 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12094 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5400 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12095 +instret:5401 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12095 + 120960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h16, addr: 'h0000000080050a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 120960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 120960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5402 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12096 +instret:5403 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12096 + 120970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h17, addr: 'h0000000080002a80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 120970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5404 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12098 +instret:5405 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12098 + 120990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 120990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 120990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 120990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 120990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5406 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12099 +instret:5407 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12099 + 121000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h00, addr: 'h0000000080050a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5408 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12100 +instret:5409 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12100 + 121010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002a88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121010 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 121020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080002b00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5410 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12102 +instret:5411 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12102 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5412 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12103 +instret:5413 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12103 + 121040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5414 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12104 +instret:5415 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12104 + 121050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002a90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002a98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5416 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12106 +instret:5417 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12106 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02a98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5418 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12107 +instret:5419 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12107 + 121080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5420 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12108 +instret:5421 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12108 + 121090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002a98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002aa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5422 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12110 +instret:5423 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12110 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02aa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5424 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12111 +instret:5425 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12111 + 121120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5426 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12112 +instret:5427 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12112 + 121130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002aa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002aa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5428 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12114 +instret:5429 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12114 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02aa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5430 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12115 +instret:5431 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12115 + 121160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5432 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12116 +instret:5433 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12116 + 121170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002aa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ab0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5434 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12118 +instret:5435 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12118 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ab0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5436 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12119 +instret:5437 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12119 + 121200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5438 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12120 +instret:5439 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12120 + 121210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002ab0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ab8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5440 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12122 +instret:5441 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12122 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ab8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5442 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12123 +instret:5443 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12123 + 121240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5444 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12124 +instret:5445 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12124 + 121250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002ab8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ac0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5446 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12126 +instret:5447 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12126 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ac0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5448 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12127 +instret:5449 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12127 + 121280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 121280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5450 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12128 +instret:5451 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12128 + 121290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121300 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050ac0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ac8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5452 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12130 +instret:5453 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12130 + 121310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ac8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5454 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12131 +instret:5455 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12131 + 121320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 121320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121330 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 121340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002b40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ad0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ad0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 121360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ad8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ad8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 121400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ae0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ae0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121460 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050ac0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 121460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121470 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 121470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050ac0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ae8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050ac8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ae8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050ad0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 121500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050ad8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +instret:5456 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12150 + 121510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050ae0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002af0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5457 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12151 + 121520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02af0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5458 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12152 +instret:5459 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12152 + 121530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002ae8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5460 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12153 +instret:5461 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12153 + 121540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5462 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12154 +instret:5463 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12154 + 121550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002af0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002af8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5464 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12155 +instret:5465 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12155 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02af8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5466 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12156 +instret:5467 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12156 + 121570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5468 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12157 +instret:5469 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12157 + 121580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002af8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5470 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12158 +instret:5471 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12158 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5472 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12159 +instret:5473 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12159 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5474 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12160 +instret:5475 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12160 + 121610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 121610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5476 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12161 +instret:5477 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12161 + 121620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5478 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12162 +instret:5479 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12162 + 121630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b00, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5480 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12163 +instret:5481 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12163 + 121640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5482 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12164 +instret:5483 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12164 + 121650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 121650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5484 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12165 +instret:5485 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12165 + 121660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121660 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5486 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12166 +instret:5487 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12166 + 121670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002b80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5488 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12167 +instret:5489 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12167 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5490 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12168 +instret:5491 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12168 + 121690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 121690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5492 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12169 +instret:5493 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12169 + 121700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5494 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12170 +instret:5495 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12170 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5496 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12171 +instret:5497 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12171 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5498 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12172 +instret:5499 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12172 + 121730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h3 + 121730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5500 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12173 +instret:5501 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12173 + 121740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5502 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12174 +instret:5503 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12174 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121790 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b00, toState: E, child: , data: tagged Invalid , id: 'h1 } + 121790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121800 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 121800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050b00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050b08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050b10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 121830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050b18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:5504 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12183 + 121840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 121840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5505 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12184 + 121850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5506 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12185 +instret:5507 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12185 + 121860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002b28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5508 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12186 +instret:5509 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12186 + 121870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5510 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12187 +instret:5511 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12187 + 121880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002b30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5512 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12188 +instret:5513 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12188 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5514 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12189 +instret:5515 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12189 + 121900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5516 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12190 +instret:5517 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12190 + 121910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5518 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12191 +instret:5519 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12191 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5520 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12192 +instret:5521 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12192 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5522 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12193 +instret:5523 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12193 + 121940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 121940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5524 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12194 +instret:5525 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12194 + 121950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5526 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12195 +instret:5527 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12195 + 121960 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b40, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5528 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12196 +instret:5529 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12196 + 121970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 121970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 121970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5530 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12197 +instret:5531 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12197 + 121980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 121980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 121980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5532 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12198 +instret:5533 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12198 + 121990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 121990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 121990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 121990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 121990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5534 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12199 +instret:5535 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12199 + 122000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002bc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5536 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12200 +instret:5537 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12200 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5538 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12201 +instret:5539 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12201 + 122020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 122020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5540 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12202 +instret:5541 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12202 + 122030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5542 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12203 +instret:5543 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12203 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5544 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12204 +instret:5545 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12204 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5546 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12205 +instret:5547 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12205 + 122060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 122060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5548 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12206 +instret:5549 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12206 + 122070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122070 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5550 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12207 +instret:5551 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12207 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122120 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b40, toState: E, child: , data: tagged Invalid , id: 'h1 } + 122120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122130 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 122130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050b40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050b48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050b50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 122160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050b58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +instret:5552 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12216 + 122170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050b60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5553 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12217 + 122180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5554 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12218 +instret:5555 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12218 + 122190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002b68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5556 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12219 +instret:5557 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12219 + 122200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5558 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12220 +instret:5559 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12220 + 122210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002b70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5560 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12221 +instret:5561 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12221 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5562 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12222 +instret:5563 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12222 + 122230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5564 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12223 +instret:5565 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12223 + 122240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002b78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5566 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12224 +instret:5567 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12224 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5568 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12225 +instret:5569 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12225 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5570 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12226 +instret:5571 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12226 + 122270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 122270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5572 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12227 +instret:5573 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12227 + 122280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5574 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12228 +instret:5575 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12228 + 122290 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050b80, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5576 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12229 +instret:5577 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12229 + 122300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5578 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12230 +instret:5579 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12230 + 122310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 122310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5580 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12231 +instret:5581 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12231 + 122320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122320 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5582 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12232 +instret:5583 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12232 + 122330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002c00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5584 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12233 +instret:5585 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12233 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5586 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12234 +instret:5587 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12234 + 122350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h0 + 122350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5588 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12235 +instret:5589 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12235 + 122360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5590 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12236 +instret:5591 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12236 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002b98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5592 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12237 +instret:5593 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12237 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02b98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5594 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12238 +instret:5595 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12238 + 122390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 122390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5596 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12239 +instret:5597 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12239 + 122400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5598 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12240 +instret:5599 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12240 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ba0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ba0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050b80, toState: E, child: , data: tagged Invalid , id: 'h1 } + 122450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 122460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050b80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ba8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050b88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ba8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050b90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 122490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050b98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:5600 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12249 + 122500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ba0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5601 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12250 + 122510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5602 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12251 +instret:5603 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12251 + 122520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ba8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5604 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12252 +instret:5605 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12252 + 122530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5606 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12253 +instret:5607 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12253 + 122540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002bb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5608 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12254 +instret:5609 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12254 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5610 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12255 +instret:5611 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12255 + 122560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5612 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12256 +instret:5613 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12256 + 122570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002bb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5614 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12257 +instret:5615 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12257 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5616 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12258 +instret:5617 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12258 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5618 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12259 +instret:5619 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12259 + 122600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 122600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5620 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12260 +instret:5621 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12260 + 122610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5622 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12261 +instret:5623 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12261 + 122620 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050bc0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5624 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12262 +instret:5625 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12262 + 122630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5626 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12263 +instret:5627 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12263 + 122640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 122640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5628 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12264 +instret:5629 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12264 + 122650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122650 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5630 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12265 +instret:5631 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12265 + 122660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002c40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5632 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12266 +instret:5633 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12266 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5634 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12267 +instret:5635 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12267 + 122680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 122680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5636 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12268 +instret:5637 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12268 + 122690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5638 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12269 +instret:5639 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12269 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5640 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12270 +instret:5641 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12270 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5642 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12271 +instret:5643 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12271 + 122720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 122720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5644 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12272 +instret:5645 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12272 + 122730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5646 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12273 +instret:5647 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12273 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002be0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02be0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122780 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050bc0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 122780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122790 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 122790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050bc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002be8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050bc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02be8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050bd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 122820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050bd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +instret:5648 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12282 + 122830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 122830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050be0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5649 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12283 + 122840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5650 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12284 +instret:5651 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12284 + 122850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002be8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5652 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12285 +instret:5653 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12285 + 122860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5654 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12286 +instret:5655 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12286 + 122870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002bf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002bf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5656 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12287 +instret:5657 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12287 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02bf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5658 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12288 +instret:5659 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12288 + 122890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5660 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12289 +instret:5661 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12289 + 122900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002bf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5662 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12290 +instret:5663 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12290 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5664 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12291 +instret:5665 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12291 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5666 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12292 +instret:5667 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12292 + 122930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 122930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5668 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12293 +instret:5669 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12293 + 122940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5670 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12294 +instret:5671 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12294 + 122950 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c00, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5672 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12295 +instret:5673 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12295 + 122960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 122960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5674 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12296 +instret:5675 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12296 + 122970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 122970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 122970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5676 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12297 +instret:5677 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12297 + 122980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 122980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 122980 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5678 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12298 +instret:5679 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12298 + 122990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 122990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 122990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002c80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 122990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5680 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12299 +instret:5681 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12299 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5682 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12300 +instret:5683 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12300 + 123010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 123010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5684 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12301 +instret:5685 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12301 + 123020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5686 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12302 +instret:5687 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12302 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5688 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12303 +instret:5689 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12303 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5690 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12304 +instret:5691 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12304 + 123050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h3 + 123050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5692 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12305 +instret:5693 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12305 + 123060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5694 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12306 +instret:5695 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12306 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123110 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c00, toState: E, child: , data: tagged Invalid , id: 'h1 } + 123110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123120 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 123120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050c00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050c08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050c10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 123150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h04, addr: 'h0000000080050c18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:5696 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12315 + 123160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5697 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12316 + 123170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5698 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12317 +instret:5699 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12317 + 123180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080002c28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5700 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12318 +instret:5701 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12318 + 123190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080050c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5702 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12319 +instret:5703 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12319 + 123200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0b, addr: 'h0000000080002c30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5704 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12320 +instret:5705 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12320 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5706 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12321 +instret:5707 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12321 + 123220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0c, addr: 'h0000000080050c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5708 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12322 +instret:5709 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12322 + 123230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123230 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5710 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12323 +instret:5711 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12323 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5712 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12324 +instret:5713 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12324 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5714 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12325 +instret:5715 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12325 + 123260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 123260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5716 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12326 +instret:5717 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12326 + 123270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5718 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12327 +instret:5719 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12327 + 123280 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c40, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5720 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12328 +instret:5721 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12328 + 123290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5722 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12329 +instret:5723 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12329 + 123300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 123300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5724 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12330 +instret:5725 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12330 + 123310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080002c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123310 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5726 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12331 +instret:5727 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12331 + 123320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002cc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5728 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12332 +instret:5729 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12332 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5730 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12333 +instret:5731 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12333 + 123340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 123340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5732 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12334 +instret:5733 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12334 + 123350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080002c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5734 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12335 +instret:5735 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12335 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5736 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12336 +instret:5737 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12336 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080050c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5738 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12337 +instret:5739 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12337 + 123380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080050c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 123380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5740 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12338 +instret:5741 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12338 + 123390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5742 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12339 +instret:5743 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12339 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123440 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c40, toState: E, child: , data: tagged Invalid , id: 'h1 } + 123440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123450 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 123450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050c40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050c48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080050c50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 123480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080050c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h14, addr: 'h0000000080050c58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +instret:5744 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12348 + 123490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050c60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5745 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12349 + 123500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5746 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12350 +instret:5747 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12350 + 123510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002c68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5748 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12351 +instret:5749 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12351 + 123520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5750 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12352 +instret:5751 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12352 + 123530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002c70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5752 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12353 +instret:5753 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12353 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5754 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12354 +instret:5755 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12354 + 123550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5756 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12355 +instret:5757 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12355 + 123560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002c78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5758 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12356 +instret:5759 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12356 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5760 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12357 +instret:5761 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12357 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5762 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12358 +instret:5763 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12358 + 123590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 123590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5764 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12359 +instret:5765 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12359 + 123600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5766 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12360 +instret:5767 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12360 + 123610 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050c80, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5768 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12361 +instret:5769 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12361 + 123620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5770 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12362 +instret:5771 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12362 + 123630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 123630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5772 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12363 +instret:5773 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12363 + 123640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h09, addr: 'h0000000080002c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123640 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5774 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12364 +instret:5775 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12364 + 123650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002d00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5776 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12365 +instret:5777 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12365 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5778 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12366 +instret:5779 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12366 + 123670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h0 + 123670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5780 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12367 +instret:5781 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12367 + 123680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0b, addr: 'h0000000080002c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123680 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5782 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12368 +instret:5783 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12368 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002c98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5784 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12369 +instret:5785 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12369 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02c98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5786 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12370 +instret:5787 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12370 + 123710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 123710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5788 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12371 +instret:5789 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12371 + 123720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0d, addr: 'h0000000080002c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5790 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12372 +instret:5791 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12372 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ca0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ca0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123770 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050c80, toState: E, child: , data: tagged Invalid , id: 'h1 } + 123770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123780 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 123780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050c80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ca8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080050c88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ca8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050c90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 123810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0c, addr: 'h0000000080050c98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:5792 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12381 + 123820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 123820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050ca0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5793 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12382 + 123830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5794 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12383 +instret:5795 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12383 + 123840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002ca8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5796 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12384 +instret:5797 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12384 + 123850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h12, addr: 'h0000000080050cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5798 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12385 +instret:5799 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12385 + 123860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h13, addr: 'h0000000080002cb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5800 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12386 +instret:5801 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12386 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5802 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12387 +instret:5803 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12387 + 123880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h0000000080050cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5804 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12388 +instret:5805 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12388 + 123890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002cb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5806 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12389 +instret:5807 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12389 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5808 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12390 +instret:5809 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12390 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5810 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12391 +instret:5811 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12391 + 123920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 123920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5812 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12392 +instret:5813 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12392 + 123930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h17, addr: 'h0000000080002cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5814 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12393 +instret:5815 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12393 + 123940 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050cc0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5816 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12394 +instret:5817 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12394 + 123950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5818 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12395 +instret:5819 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12395 + 123960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 123960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 123960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5820 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12396 +instret:5821 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12396 + 123970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h01, addr: 'h0000000080002cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 123970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 123970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5822 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12397 +instret:5823 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12397 + 123980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 123980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 123980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002d40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 123980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5824 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12398 +instret:5825 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12398 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 123990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080050cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5826 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12399 +instret:5827 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12399 + 124000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080050cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 124000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5828 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12400 +instret:5829 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12400 + 124010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h03, addr: 'h0000000080002cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5830 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12401 +instret:5831 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12401 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5832 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12402 +instret:5833 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12402 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5834 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12403 +instret:5835 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12403 + 124040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 124040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5836 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12404 +instret:5837 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12404 + 124050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5838 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12405 +instret:5839 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12405 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ce0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ce0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124100 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050cc0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 124100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124110 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 124110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h16, addr: 'h0000000080050cc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ce8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050cc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ce8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080050cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080050cd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 124140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050cd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +instret:5840 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12414 + 124150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050ce0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5841 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12415 + 124160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cf0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5842 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12416 +instret:5843 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12416 + 124170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h09, addr: 'h0000000080002ce8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5844 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12417 +instret:5845 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12417 + 124180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5846 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12418 +instret:5847 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12418 + 124190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0b, addr: 'h0000000080002cf0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002cf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5848 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12419 +instret:5849 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12419 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02cf8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5850 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12420 +instret:5851 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12420 + 124210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0c, addr: 'h0000000080050cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5852 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12421 +instret:5853 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12421 + 124220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002cf8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5854 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12422 +instret:5855 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12422 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5856 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12423 +instret:5857 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12423 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5858 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12424 +instret:5859 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12424 + 124250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 124250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5860 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12425 +instret:5861 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12425 + 124260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0f, addr: 'h0000000080002d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5862 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12426 +instret:5863 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12426 + 124270 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d00, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124270 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5864 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12427 +instret:5865 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12427 + 124280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5866 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12428 +instret:5867 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12428 + 124290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 124290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5868 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12429 +instret:5869 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12429 + 124300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h11, addr: 'h0000000080002d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124300 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5870 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12430 +instret:5871 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12430 + 124310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002d80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124310 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5872 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12431 +instret:5873 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12431 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5874 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12432 +instret:5875 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12432 + 124330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 124330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5876 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12433 +instret:5877 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12433 + 124340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h13, addr: 'h0000000080002d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5878 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12434 +instret:5879 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12434 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5880 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12435 +instret:5881 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12435 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5882 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12436 +instret:5883 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12436 + 124370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h3 + 124370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5884 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12437 +instret:5885 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12437 + 124380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h15, addr: 'h0000000080002d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5886 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12438 +instret:5887 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12438 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124420 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124430 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d00, toState: E, child: , data: tagged Invalid , id: 'h1 } + 124430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124440 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 124440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0e, addr: 'h0000000080050d00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h10, addr: 'h0000000080050d08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h12, addr: 'h0000000080050d10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 124470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h14, addr: 'h0000000080050d18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:5888 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12447 + 124480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5889 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12448 + 124490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5890 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12449 +instret:5891 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12449 + 124500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080002d28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5892 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12450 +instret:5893 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12450 + 124510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h0000000080050d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5894 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12451 +instret:5895 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12451 + 124520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080002d30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5896 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12452 +instret:5897 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12452 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5898 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12453 +instret:5899 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12453 + 124540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h0000000080050d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5900 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12454 +instret:5901 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12454 + 124550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5902 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12455 +instret:5903 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12455 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5904 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12456 +instret:5905 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12456 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5906 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12457 +instret:5907 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12457 + 124580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 124580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5908 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12458 +instret:5909 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12458 + 124590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h07, addr: 'h0000000080002d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5910 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12459 +instret:5911 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12459 + 124600 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d40, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5912 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12460 +instret:5913 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12460 + 124610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5914 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12461 +instret:5915 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12461 + 124620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 124620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5916 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12462 +instret:5917 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12462 + 124630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124630 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5918 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12463 +instret:5919 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12463 + 124640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002dc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5920 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12464 +instret:5921 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12464 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5922 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12465 +instret:5923 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12465 + 124660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 124660 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5924 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12466 +instret:5925 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12466 + 124670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080002d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5926 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12467 +instret:5927 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12467 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5928 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12468 +instret:5929 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12468 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5930 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12469 +instret:5931 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12469 + 124700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 124700 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5932 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12470 +instret:5933 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12470 + 124710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080002d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5934 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12471 +instret:5935 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12471 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d40, toState: E, child: , data: tagged Invalid , id: 'h1 } + 124760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 124770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h06, addr: 'h0000000080050d40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h08, addr: 'h0000000080050d48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050d50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 124800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h0000000080050d58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +instret:5936 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12480 + 124810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 124810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050d60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5937 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12481 + 124820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5938 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12482 +instret:5939 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12482 + 124830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002d68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5940 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12483 +instret:5941 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12483 + 124840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5942 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12484 +instret:5943 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12484 + 124850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002d70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5944 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12485 +instret:5945 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12485 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5946 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12486 +instret:5947 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12486 + 124870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5948 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12487 +instret:5949 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12487 + 124880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002d78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5950 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12488 +instret:5951 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12488 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5952 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12489 +instret:5953 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12489 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5954 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12490 +instret:5955 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12490 + 124910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 124910 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5956 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12491 +instret:5957 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12491 + 124920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5958 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12492 +instret:5959 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12492 + 124930 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050d80, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124930 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5960 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12493 +instret:5961 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12493 + 124940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5962 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12494 +instret:5963 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12494 + 124950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 124950 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5964 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12495 +instret:5965 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12495 + 124960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h01, addr: 'h0000000080002d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 124960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 124960 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:5966 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12496 +instret:5967 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12496 + 124970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 124970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002e00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 124970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5968 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12497 +instret:5969 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12497 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 124980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080050d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5970 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12498 +instret:5971 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12498 + 124990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 124990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080050d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 124990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h0 + 124990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5972 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12499 +instret:5973 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12499 + 125000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h03, addr: 'h0000000080002d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5974 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12500 +instret:5975 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12500 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002d98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5976 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12501 +instret:5977 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12501 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02d98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5978 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12502 +instret:5979 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12502 + 125030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 125030 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5980 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12503 +instret:5981 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12503 + 125040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080002d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5982 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12504 +instret:5983 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12504 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002da0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02da0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125090 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050d80, toState: E, child: , data: tagged Invalid , id: 'h1 } + 125090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125100 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 125100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050d80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002da8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080050d88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02da8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125110 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080050d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h02, addr: 'h0000000080050d90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 125130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080050d98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:5984 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12513 + 125140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050da0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002db0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5985 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12514 + 125150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02db0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5986 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12515 +instret:5987 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12515 + 125160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h09, addr: 'h0000000080002da8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5988 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12516 +instret:5989 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12516 + 125170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080050db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5990 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12517 +instret:5991 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12517 + 125180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0b, addr: 'h0000000080002db0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002db8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:5992 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12518 +instret:5993 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12518 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02db8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:5994 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12519 +instret:5995 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12519 + 125200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0c, addr: 'h0000000080050db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:5996 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12520 +instret:5997 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12520 + 125210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002db8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:5998 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12521 +instret:5999 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12521 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6000 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12522 +instret:6001 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12522 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6002 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12523 +instret:6003 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12523 + 125240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 125240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6004 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12524 +instret:6005 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12524 + 125250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080002dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6006 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12525 +instret:6007 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12525 + 125260 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050dc0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6008 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12526 +instret:6009 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12526 + 125270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6010 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12527 +instret:6011 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12527 + 125280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 125280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6012 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12528 +instret:6013 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12528 + 125290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h11, addr: 'h0000000080002dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125290 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6014 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12529 +instret:6015 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12529 + 125300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002e40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6016 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12530 +instret:6017 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12530 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6018 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12531 +instret:6019 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12531 + 125320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 125320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6020 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12532 +instret:6021 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12532 + 125330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h13, addr: 'h0000000080002dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6022 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12533 +instret:6023 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12533 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002dd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6024 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12534 +instret:6025 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12534 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02dd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6026 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12535 +instret:6027 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12535 + 125360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 125360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6028 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12536 +instret:6029 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12536 + 125370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6030 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12537 +instret:6031 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12537 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002de0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02de0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125420 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050dc0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 125420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125430 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 125430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0e, addr: 'h0000000080050dc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002de8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050dc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02de8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h12, addr: 'h0000000080050dd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 125460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080050dd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +instret:6032 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12546 + 125470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050de0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002df0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6033 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12547 + 125480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02df0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6034 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12548 +instret:6035 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12548 + 125490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080002de8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6036 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12549 +instret:6037 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12549 + 125500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h02, addr: 'h0000000080050df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6038 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12550 +instret:6039 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12550 + 125510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h03, addr: 'h0000000080002df0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002df8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6040 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12551 +instret:6041 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12551 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02df8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6042 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12552 +instret:6043 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12552 + 125530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h04, addr: 'h0000000080050df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6044 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12553 +instret:6045 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12553 + 125540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002df8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6046 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12554 +instret:6047 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12554 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6048 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12555 +instret:6049 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12555 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6050 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12556 +instret:6051 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12556 + 125570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 125570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6052 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12557 +instret:6053 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12557 + 125580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h07, addr: 'h0000000080002e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6054 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12558 +instret:6055 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12558 + 125590 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e00, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125590 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6056 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12559 +instret:6057 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12559 + 125600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6058 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12560 +instret:6059 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12560 + 125610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 + 125610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6060 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12561 +instret:6061 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12561 + 125620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h09, addr: 'h0000000080002e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125620 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6062 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12562 +instret:6063 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12562 + 125630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002e80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6064 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12563 +instret:6065 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12563 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6066 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12564 +instret:6067 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12564 + 125650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 + 125650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6068 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12565 +instret:6069 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12565 + 125660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6070 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12566 +instret:6071 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12566 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6072 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12567 +instret:6073 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12567 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6074 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12568 +instret:6075 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12568 + 125690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h3 + 125690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6076 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12569 +instret:6077 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12569 + 125700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0d, addr: 'h0000000080002e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6078 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12570 +instret:6079 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12570 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125740 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125750 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e00, toState: E, child: , data: tagged Invalid , id: 'h1 } + 125750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125760 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 125760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080050e00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h0000000080050e08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050e10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 125790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0c, addr: 'h0000000080050e18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 +instret:6080 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12579 + 125800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 125800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6081 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12580 + 125810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6082 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12581 +instret:6083 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12581 + 125820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080002e28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6084 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12582 +instret:6085 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12582 + 125830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h12, addr: 'h0000000080050e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125830 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6086 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12583 +instret:6087 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12583 + 125840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h13, addr: 'h0000000080002e30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6088 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12584 +instret:6089 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12584 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6090 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12585 +instret:6091 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12585 + 125860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080050e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6092 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12586 +instret:6093 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12586 + 125870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125870 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6094 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12587 +instret:6095 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12587 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6096 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12588 +instret:6097 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12588 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6098 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12589 +instret:6099 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12589 + 125900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 125900 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6100 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12590 +instret:6101 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12590 + 125910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125910 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080002e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6102 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12591 +instret:6103 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12591 + 125920 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e40, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125920 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6104 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12592 +instret:6105 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12592 + 125930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6106 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12593 +instret:6107 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12593 + 125940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 + 125940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6108 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12594 +instret:6109 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12594 + 125950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h01, addr: 'h0000000080002e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 125950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6110 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12595 +instret:6111 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12595 + 125960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080002ec0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 125960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6112 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12596 +instret:6113 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12596 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 125970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6114 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12597 +instret:6115 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12597 + 125980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 125980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 125980 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6116 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12598 +instret:6117 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12598 + 125990 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 125990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125990 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 125990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080002e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 125990 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6118 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12599 +instret:6119 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12599 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6120 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12600 +instret:6121 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12600 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6122 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12601 +instret:6123 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12601 + 126020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h4 + 126020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6124 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12602 +instret:6125 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12602 + 126030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h05, addr: 'h0000000080002e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6126 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12603 +instret:6127 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12603 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126070 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126080 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e40, toState: E, child: , data: tagged Invalid , id: 'h1 } + 126080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126090 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 126090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080050e40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080050e48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h02, addr: 'h0000000080050e50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 126120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080050e58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +instret:6128 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12612 + 126130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050e60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6129 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12613 + 126140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6130 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12614 +instret:6131 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12614 + 126150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002e68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6132 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12615 +instret:6133 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12615 + 126160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6134 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12616 +instret:6135 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12616 + 126170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002e70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6136 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12617 +instret:6137 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12617 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6138 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12618 +instret:6139 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12618 + 126190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6140 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12619 +instret:6141 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12619 + 126200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002e78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126200 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6142 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12620 +instret:6143 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12620 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6144 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12621 +instret:6145 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12621 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126220 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6146 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12622 +instret:6147 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12622 + 126230 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126230 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 126230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6148 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12623 +instret:6149 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12623 + 126240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6150 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12624 +instret:6151 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12624 + 126250 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050e80, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126250 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6152 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12625 +instret:6153 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12625 + 126260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6154 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12626 +instret:6155 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12626 + 126270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 126270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6156 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12627 +instret:6157 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12627 + 126280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h11, addr: 'h0000000080002e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126280 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6158 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12628 +instret:6159 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12628 + 126290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080002f00, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6160 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12629 +instret:6161 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12629 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6162 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12630 +instret:6163 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12630 + 126310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h0 + 126310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6164 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12631 +instret:6165 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12631 + 126320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h0000000080002e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6166 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12632 +instret:6167 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12632 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002e98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6168 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12633 +instret:6169 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12633 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02e98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6170 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12634 +instret:6171 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12634 + 126350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h1 + 126350 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6172 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12635 +instret:6173 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12635 + 126360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h15, addr: 'h0000000080002e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6174 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12636 +instret:6175 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12636 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ea0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ea0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126410 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050e80, toState: E, child: , data: tagged Invalid , id: 'h1 } + 126410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 126420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050e80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ea8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h10, addr: 'h0000000080050e88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ea8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126430 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h12, addr: 'h0000000080050e90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126440 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 126450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h14, addr: 'h0000000080050e98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 +instret:6176 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12645 + 126460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050ea0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002eb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6177 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12646 + 126470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02eb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6178 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12647 +instret:6179 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12647 + 126480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h0000000080002ea8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6180 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12648 +instret:6181 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12648 + 126490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080050eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6182 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12649 +instret:6183 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12649 + 126500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h03, addr: 'h0000000080002eb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002eb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6184 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12650 +instret:6185 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12650 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02eb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6186 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12651 +instret:6187 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12651 + 126520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h04, addr: 'h0000000080050eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126520 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6188 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12652 +instret:6189 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12652 + 126530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h05, addr: 'h0000000080002eb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6190 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12653 +instret:6191 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12653 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ec0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6192 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12654 +instret:6193 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12654 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ec0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6194 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12655 +instret:6195 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12655 + 126560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 126560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6196 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12656 +instret:6197 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12656 + 126570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h0000000080002ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6198 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12657 +instret:6199 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12657 + 126580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080050ec0, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ec8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126580 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6200 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12658 +instret:6201 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12658 + 126590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080050f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126590 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ec8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6202 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12659 +instret:6203 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12659 + 126600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 + 126600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6204 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12660 +instret:6205 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12660 + 126610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080002ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126610 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6206 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12661 +instret:6207 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12661 + 126620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080002f40, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ed0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6208 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12662 +instret:6209 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12662 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ed0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126630 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6210 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12663 +instret:6211 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12663 + 126640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 126640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6212 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12664 +instret:6213 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12664 + 126650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h0000000080002ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6214 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12665 +instret:6215 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12665 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ed8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6216 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12666 +instret:6217 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12666 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ed8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126670 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6218 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12667 +instret:6219 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12667 + 126680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h0 + 126680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6220 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12668 +instret:6221 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12668 + 126690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6222 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12669 +instret:6223 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12669 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ee0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: S, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h2 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ee0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126740 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080050ec0, toState: E, child: , data: tagged Invalid , id: 'h1 } + 126740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0f, addr: 'h0000000080002ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126750 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 126750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h06, addr: 'h0000000080050ec0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126750 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ee8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050ec8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126760 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ee8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080050ed0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 126780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050ed8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 +instret:6224 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12678 + 126790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 126790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080050ee0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ef0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6225 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [0]] 12679 + 126800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080050ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ef0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6226 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12680 +instret:6227 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12680 + 126810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h11, addr: 'h0000000080002ee8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6228 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12681 +instret:6229 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12681 + 126820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080050ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6230 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12682 +instret:6231 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12682 + 126830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080002ef0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ef8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6232 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12683 +instret:6233 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12683 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ef8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6234 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12684 +instret:6235 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12684 + 126850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h14, addr: 'h0000000080050ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6236 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12685 +instret:6237 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12685 + 126860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080002ef8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6238 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12686 +instret:6239 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12686 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6240 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12687 +instret:6241 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12687 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f00, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6242 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12688 +instret:6243 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12688 + 126890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h16, addr: 'h0000000080050f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6244 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12689 +instret:6245 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12689 + 126900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h17, addr: 'h0000000080002f00, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6246 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12690 +instret:6247 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12690 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6248 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12691 +instret:6249 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12691 + 126920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080050f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f08, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6250 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12692 +instret:6251 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12692 + 126930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080050f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6252 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12693 +instret:6253 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12693 + 126940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h01, addr: 'h0000000080002f08, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126940 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6254 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12694 +instret:6255 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12694 + 126950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080002f80, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 126950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6256 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12695 +instret:6257 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12695 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f10, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 126960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6258 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12696 +instret:6259 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12696 + 126970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h02, addr: 'h0000000080050f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 126970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 126970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6260 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12697 +instret:6261 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12697 + 126980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 126980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 126980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h03, addr: 'h0000000080002f10, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 126980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6262 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12698 +instret:6263 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12698 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6264 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12699 +instret:6265 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12699 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f18, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6266 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12700 +instret:6267 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12700 + 127010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h04, addr: 'h0000000080050f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6268 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12701 +instret:6269 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12701 + 127020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h05, addr: 'h0000000080002f18, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6270 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12702 +instret:6271 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12702 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6272 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12703 +instret:6273 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12703 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f20, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080050f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6274 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12704 +instret:6275 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12704 + 127050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080050f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h06, addr: 'h0000000080050f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6276 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12705 +instret:6277 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12705 + 127060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080002f20, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6278 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12706 +instret:6279 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12706 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6280 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12707 +instret:6281 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12707 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f28, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6282 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12708 +instret:6283 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12708 + 127090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h08, addr: 'h0000000080050f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6284 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12709 +instret:6285 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12709 + 127100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h09, addr: 'h0000000080002f28, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6286 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12710 +instret:6287 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12710 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6288 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12711 +instret:6289 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12711 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f30, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6290 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12712 +instret:6291 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12712 + 127130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080050f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6292 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12713 +instret:6293 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12713 + 127140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0b, addr: 'h0000000080002f30, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6294 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12714 +instret:6295 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12714 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6296 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12715 +instret:6297 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12715 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f38, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6298 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12716 +instret:6299 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12716 + 127170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080050f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6300 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12717 +instret:6301 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12717 + 127180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0d, addr: 'h0000000080002f38, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6302 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12718 +instret:6303 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12718 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6304 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12719 +instret:6305 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12719 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f40, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080050f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6306 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12720 +instret:6307 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12720 + 127210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080050f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0e, addr: 'h0000000080050f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127210 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6308 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12721 +instret:6309 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12721 + 127220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0f, addr: 'h0000000080002f40, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6310 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12722 +instret:6311 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12722 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127230 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6312 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12723 +instret:6313 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12723 + 127240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 127240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080050fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 127240 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f48, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6314 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12724 +instret:6315 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12724 + 127250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h10, addr: 'h0000000080050f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127250 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127250 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6316 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12725 +instret:6317 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12725 + 127260 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127260 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080002f48, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127260 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127260 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6318 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12726 +instret:6319 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12726 + 127270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 127270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080002fc0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 127270 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6320 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12727 +instret:6321 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12727 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f50, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127280 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6322 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12728 +instret:6323 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12728 + 127290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127290 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127290 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6324 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12729 +instret:6325 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12729 + 127300 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127300 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002f50, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127300 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6326 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12730 +instret:6327 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12730 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6328 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12731 +instret:6329 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12731 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f58, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127320 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6330 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12732 +instret:6331 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12732 + 127330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6332 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12733 +instret:6333 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12733 + 127340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002f58, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6334 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12735 +instret:6335 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12735 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f60, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6336 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12736 +instret:6337 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12736 + 127370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6338 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12737 +instret:6339 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12737 + 127380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002f60, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6340 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12739 +instret:6341 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12739 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f68, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6342 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12740 +instret:6343 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12740 + 127410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6344 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12741 +instret:6345 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12741 + 127420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002f68, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6346 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12743 +instret:6347 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12743 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f70, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6348 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12744 +instret:6349 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12744 + 127450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127450 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127450 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6350 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12745 +instret:6351 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12745 + 127460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002f70, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6352 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12747 +instret:6353 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12747 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f78, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6354 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12748 +instret:6355 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12748 + 127490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127490 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6356 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12749 +instret:6357 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12749 + 127500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002f78, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6358 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12751 +instret:6359 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12751 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f80, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6360 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12752 +instret:6361 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12752 + 127530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127530 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6362 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12753 +instret:6363 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12753 + 127540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002f80, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6364 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12755 +instret:6365 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12755 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f88, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127560 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6366 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12756 +instret:6367 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12756 + 127570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6368 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12757 +instret:6369 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12757 + 127580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002f88, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6370 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12759 +instret:6371 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12759 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f90, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6372 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12760 +instret:6373 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12760 + 127610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127610 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127610 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6374 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12761 +instret:6375 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12761 + 127620 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127620 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002f90, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127620 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002f98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6376 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12763 +instret:6377 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12763 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02f98, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6378 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12764 +instret:6379 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12764 + 127650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127650 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6380 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12765 +instret:6381 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12765 + 127660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002f98, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6382 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12767 +instret:6383 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12767 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fa0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6384 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12768 +instret:6385 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12768 + 127690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h0000000080050fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127690 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127690 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6386 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12769 +instret:6387 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12769 + 127700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h0000000080002fa0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6388 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12771 +instret:6389 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12771 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fa8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6390 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12772 +instret:6391 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12772 + 127730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h10, addr: 'h0000000080050fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6392 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12773 +instret:6393 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12773 + 127740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h11, addr: 'h0000000080002fa8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6394 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12775 +instret:6395 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12775 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fb0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127760 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6396 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12776 +instret:6397 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12776 + 127770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080050fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127770 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6398 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12777 +instret:6399 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12777 + 127780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h13, addr: 'h0000000080002fb0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6400 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12779 +instret:6401 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12779 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fb8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127800 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6402 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12780 +instret:6403 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12780 + 127810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h14, addr: 'h0000000080050fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127810 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6404 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12781 +instret:6405 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12781 + 127820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h15, addr: 'h0000000080002fb8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127820 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6406 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12783 +instret:6407 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12783 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fc0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127840 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6408 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12784 +instret:6409 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12784 + 127850 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127850 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080050fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127850 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6410 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12785 +instret:6411 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12785 + 127860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h0000000080002fc0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127860 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6412 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12787 +instret:6413 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12787 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fc8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127880 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6414 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12788 +instret:6415 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12788 + 127890 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127890 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080050fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127890 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127890 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6416 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12789 +instret:6417 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12789 + 127900 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127900 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h0000000080002fc8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127900 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6418 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12791 +instret:6419 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12791 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fd0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127920 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6420 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12792 +instret:6421 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12792 + 127930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h0000000080050fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6422 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12793 +instret:6423 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12793 + 127940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080002fd0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6424 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12795 +instret:6425 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12795 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fd8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 127960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6426 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12796 +instret:6427 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12796 + 127970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h04, addr: 'h0000000080050fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 127970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 127970 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6428 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12797 +instret:6429 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12797 + 127980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 127980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 127980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h05, addr: 'h0000000080002fd8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 127980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fe0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6430 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12799 +instret:6431 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12799 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fe0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 128000 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6432 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12800 +instret:6433 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12800 + 128010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h06, addr: 'h0000000080050fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 128010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6434 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12801 +instret:6435 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12801 + 128020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h07, addr: 'h0000000080002fe0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002fe8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6436 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12803 +instret:6437 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12803 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02fe8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 128040 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6438 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12804 +instret:6439 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12804 + 128050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h08, addr: 'h0000000080050fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 128050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6440 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12805 +instret:6441 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12805 + 128060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h09, addr: 'h0000000080002fe8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ff0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6442 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12807 +instret:6443 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12807 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ff0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 128080 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6444 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12808 +instret:6445 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12808 + 128090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080050ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 128090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6446 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12809 +instret:6447 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12809 + 128100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0b, addr: 'h0000000080002ff0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h0000002, ppn: 'h00000080050, pteType: PTEType { dirty: False, accessed: True, global: False, user: True, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h0, asid: 'h0 } r : TlbReq { addr: 'h0000000000002ff8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6448 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12811 +instret:6449 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12811 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe02ff8, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 128120 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } +instret:6450 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12812 +instret:6451 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12812 + 128130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h3, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040028, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0c, addr: 'h0000000080050ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdedc } + 128130 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 128130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } +instret:6452 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12813 +instret:6453 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12813 + 128140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040001, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 128140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 128140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0d, addr: 'h0000000080002ff8, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hdea0 } + 128140 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6454 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12815 +instret:6455 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12815 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: True, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe03000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6456 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12816 +instret:6457 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12816 +instret:6458 PC:0x1ffff000000000000ffffffffffe0213c instr:0x0007b683 iType:Ld [doCommitNormalInst [0]] 12818 +instret:6459 PC:0x1ffff000000000000ffffffffffe02140 instr:0x0005b703 iType:Ld [doCommitNormalInst [1]] 12818 +instret:6460 PC:0x1ffff000000000000ffffffffffe02144 instr:0x00e69863 iType:Br [doCommitNormalInst [0]] 12820 +instret:6461 PC:0x1ffff000000000000ffffffffffe02148 instr:0x00878793 iType:Alu [doCommitNormalInst [1]] 12820 +instret:6462 PC:0x1ffff000000000000ffffffffffe0214c instr:0x00858593 iType:Alu [doCommitNormalInst [0]] 12821 +instret:6463 PC:0x1ffff000000000000ffffffffffe02150 instr:0xff07e6e3 iType:Br [doCommitNormalInst [1]] 12821 + 128260 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080007018, toState: S, child: } +instret:6464 PC:0x1ffff000000000000ffffffffffe02154 instr:0x40a78533 iType:Alu [doCommitNormalInst [0]] 12826 + 128270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080007018, toState: S, child: } + 128270 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:6465 PC:0x1ffff000000000000ffffffffffe02158 instr:0x40a60633 iType:Alu [doCommitNormalInst [0]] 12827 +instret:6466 PC:0x1ffff000000000000ffffffffffe0215c instr:0x00078513 iType:Alu [doCommitNormalInst [1]] 12827 + 128280 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080007018, toState: S, child: } ; CRsMsg { addr: 'h0000000080007018, toState: S, data: tagged Invalid , child: } +instret:6467 PC:0x1ffff000000000000ffffffffffe02160 instr:0x00c58633 iType:Alu [doCommitNormalInst [0]] 12828 +instret:6468 PC:0x1ffff000000000000ffffffffffe02164 instr:0x0140006f iType:J [doCommitNormalInst [1]] 12828 +instret:6469 PC:0x1ffff000000000000ffffffffffe02178 instr:0x00150513 iType:Alu [doCommitNormalInst [0]] 12829 +instret:6470 PC:0x1ffff000000000000ffffffffffe0217c instr:0xfec596e3 iType:Br [doCommitNormalInst [1]] 12829 + 128320 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } + 128330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } + 128330 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 128340 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h0000000080002180, toState: S, child: } ; CRsMsg { addr: 'h0000000080002180, toState: S, data: tagged Invalid , child: } +instret:6471 PC:0x1ffff000000000000ffffffffffe02180 instr:0x00000513 iType:Alu [doCommitNormalInst [0]] 12849 +instret:6472 PC:0x1ffff000000000000ffffffffffe02184 instr:0x00008067 iType:Jr [doCommitNormalInst [1]] 12849 + 128540 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h00000000800027ac, toState: S, child: } + 128550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h00000000800027ac, toState: S, child: } + 128550 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 128560 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h00000000800027ac, toState: S, child: } ; CRsMsg { addr: 'h00000000800027ac, toState: S, data: tagged Invalid , child: } +instret:6473 PC:0x1ffff000000000000ffffffffffe027ac instr:0x00050e63 iType:Br [doCommitNormalInst [0]] 12872 + 128760 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } + 128770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } + 128770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 128780 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h00000000800027c0, toState: S, child: } ; CRsMsg { addr: 'h00000000800027c0, toState: S, data: tagged Invalid , child: } +instret:6474 PC:0x1ffff000000000000ffffffffffe027c8 instr:0x008487b3 iType:Alu [doCommitNormalInst [0]] 12895 +instret:6475 PC:0x1ffff000000000000ffffffffffe027cc instr:0x100d1073 iType:Csr [doCommitSystemInst] 12901 + 129040 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002800, toState: S, child: } + 129050 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002800, toState: S, child: } + 129050 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 129060 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002800, toState: S, child: } ; CRsMsg { addr: 'h0000000080002800, toState: S, data: tagged Invalid , child: } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08410, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } + 129210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd830 } + 129220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd830 } + 129220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0e, addr: 'h00000000800087e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd830 } + 129220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:6476 PC:0x1ffff000000000000ffffffffffe027d0 instr:0x000a3703 iType:Ld [doCommitNormalInst [0]] 12925 +instret:6477 PC:0x1ffff000000000000ffffffffffe027d4 instr:0x0007b023 iType:St [doCommitNormalInst [1]] 12925 + 129260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd834 } + 129280 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h2 ; PRqMsg { addr: 'h000000008000275c, toState: S, child: } + 129280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd834 } + 129280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080008410, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd834 } + 129280 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6478 PC:0x1ffff000000000000ffffffffffe027d8 instr:0xf6071ce3 iType:Br [doCommitNormalInst [0]] 12928 + 129290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h2 ; PRqMsg { addr: 'h000000008000275c, toState: S, child: } + 129290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 129300 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h2 ; PRqMsg { addr: 'h000000008000275c, toState: S, child: } ; CRsMsg { addr: 'h000000008000275c, toState: S, data: tagged Invalid , child: } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe083e8, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087e0, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:6479 PC:0x1ffff000000000000ffffffffffe02750 instr:0x00f73423 iType:St [doCommitNormalInst [0]] 12947 +instret:6480 PC:0x1ffff000000000000ffffffffffe02754 instr:0x00006717 iType:Auipc [doCommitNormalInst [1]] 12947 + 129480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b0 } +instret:6481 PC:0x1ffff000000000000ffffffffffe02758 instr:0x08f73623 iType:St [doCommitNormalInst [0]] 12948 +instret:6482 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 12948 + 129490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b0 } + 129490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h00000000800083e8, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b0 } + 129490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6483 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 12949 + 129500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b8 } +instret:6484 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 12950 +instret:6485 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 12950 + 129510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b8 } + 129510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h00000000800087e0, toState: M, op: St, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd8b8 } + 129510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08420, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6486 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 12951 + 129520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080008420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6487 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 12952 + 129530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080008420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0f, addr: 'h0000000080008420, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07018, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 129550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080007018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: S, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080007018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6488 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 12956 + 129580 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080007018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } ; L1CRqSlot { way: 'h1, cs: S, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007018, fromState: S, toState: E, canUpToE: True, id: 'h1, child: , isPrefetchRq: False } +instret:6489 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 12959 + 129650 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007018, toState: E, child: , data: tagged Invalid , id: 'h1 } + 129660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129660 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 129660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080007018, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6490 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 12969 +instret:6491 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 12970 +instret:6492 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 12971 +instret:6493 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 12971 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08430, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6494 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 12972 + 129730 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6495 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 12973 + 129740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h0000000080008430, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 129760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008470, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 129770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008470, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 129770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008470, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 129770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07020, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 129770 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800084b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6496 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 12977 + 129780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800084b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 129780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 129780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080007020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129800 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800084b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800084b0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 129800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080007020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h11, addr: 'h0000000080007020, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 129800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6497 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 12980 +instret:6498 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 12990 +instret:6499 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 12991 +instret:6500 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 12992 +instret:6501 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 12992 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08440, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6502 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 12993 + 129940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080008440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6503 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 12994 + 129950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080008440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 129950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h0000000080008440, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 129950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 129970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800084c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 129980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 129980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800084c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 129980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07028, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6504 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 12998 + 129990 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080007028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800084c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800084c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 130010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080007028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h0000000080007028, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6505 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13001 + 130030 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080007068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 130040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080007068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 130040 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800070a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 130050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800070a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 130060 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080007068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080007068, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } + 130070 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800070a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800070a8, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +instret:6506 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 13011 +instret:6507 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13012 +instret:6508 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 13013 +instret:6509 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 13013 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08450, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6510 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 13014 + 130150 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080008450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6511 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13015 + 130160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080008450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h12, addr: 'h0000000080008450, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07030, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6512 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13019 + 130200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080007030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080007030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h13, addr: 'h0000000080007030, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6513 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13022 + 130280 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800084b0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 130290 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130290 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 130290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800084b0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130290 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6514 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 13032 +instret:6515 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13033 +instret:6516 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 13034 +instret:6517 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 13034 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08460, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6518 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 13035 + 130360 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6519 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13036 + 130370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008460, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130370 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07038, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6520 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13040 + 130410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080007038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h1, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080007038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080007038, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6521 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13043 +instret:6522 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 13053 +instret:6523 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13054 +instret:6524 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 13055 +instret:6525 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 13055 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08470, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6526 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 13056 + 130570 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080008470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6527 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13057 + 130580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080008470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h14, addr: 'h0000000080008470, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130580 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130590 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800084c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 130600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130600 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 130600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800084c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130600 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe07040, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6528 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13061 + 130620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080007040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080007040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:6529 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13064 +instret:6530 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [0]] 13074 +instret:6531 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13075 +instret:6532 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [0]] 13076 +instret:6533 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [1]] 13076 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08480, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6534 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [0]] 13077 +instret:6535 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13078 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08490, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 130820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080008490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080008490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h16, addr: 'h0000000080008490, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130830 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 130870 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800084a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130880 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800084a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130880 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h17, addr: 'h00000000800084a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130880 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130900 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080007068, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 130910 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130910 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 130910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080007068, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130910 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 130910 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800084e0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 130920 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080007040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130920 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 130920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080007040, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd868 } + 130920 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130930 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800084e0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130930 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800084e0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130930 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800084b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800084b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h00000000800084b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130940 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008480, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 130950 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008520, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 130960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008520, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 130960 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800084c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800084c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 130970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800084c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 130970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 130970 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800070c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 130980 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008520, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008520, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 130980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 130980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800070c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 130980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6536 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13098 + 131000 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800070c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800070c0, fromState: I, toState: S, canUpToE: True, id: 'h0, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6537 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13100 +instret:6538 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13100 + 131010 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800084d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6539 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13101 +instret:6540 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13101 + 131020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800084d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 131020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h02, addr: 'h00000000800084d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6541 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13102 +instret:6542 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13102 +instret:6543 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13103 +instret:6544 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13103 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6545 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13104 +instret:6546 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13104 + 131050 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800084e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6547 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13105 +instret:6548 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13105 + 131060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800084e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 131060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h00000000800084e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131060 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6549 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13106 +instret:6550 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13106 +instret:6551 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13107 +instret:6552 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13107 +instret:6553 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13108 +instret:6554 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13108 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe084f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6555 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13109 +instret:6556 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13109 + 131100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800084f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6557 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13110 +instret:6558 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13110 + 131110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800084f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 131110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h04, addr: 'h00000000800084f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6559 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13111 +instret:6560 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13111 +instret:6561 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13112 +instret:6562 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13112 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08500, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 131130 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008530, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6563 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13113 +instret:6564 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13113 + 131140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h0000000080008530, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 131140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080008500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6565 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13114 +instret:6566 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13114 + 131150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080008500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 + 131150 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008570, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6567 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13115 +instret:6568 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13115 + 131160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008570, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6569 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13116 +instret:6570 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13116 +instret:6571 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13117 +instret:6572 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13117 + 131180 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008570, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008570, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08510, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6573 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13118 +instret:6574 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13118 + 131190 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080008510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6575 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13119 +instret:6576 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13119 + 131200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080008510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h3 +instret:6577 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13120 +instret:6578 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13120 + 131210 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800070a8, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } +instret:6579 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13121 +instret:6580 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13121 + 131220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131220 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 131220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h00000000800070a8, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131220 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08520, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6581 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13122 +instret:6582 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13122 + 131230 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080008520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6583 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13123 +instret:6584 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13123 + 131240 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080008520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131240 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h2 +instret:6585 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13124 +instret:6586 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13124 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08530, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6587 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13125 +instret:6588 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13125 + 131260 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080008530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6589 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13126 +instret:6590 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13126 + 131270 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080008530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131270 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h4 +instret:6591 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13127 +instret:6592 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13127 +instret:6593 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13128 +instret:6594 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13128 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08540, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6595 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13129 +instret:6596 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13129 + 131300 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080008540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6597 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13130 +instret:6598 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13130 + 131310 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080008540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131310 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:6599 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13131 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08550, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08560, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08570, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 131520 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008520, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 131530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131530 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 131530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008520, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 131540 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080008500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131540 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 131540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h05, addr: 'h0000000080008500, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131540 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 131540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080008510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 131550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h06, addr: 'h0000000080008510, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 131560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080008520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 131560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080008520, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131560 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 131570 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080008530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131570 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 131570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h08, addr: 'h0000000080008530, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131570 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6600 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13157 + 131580 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131580 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 + 131580 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080008560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131590 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080008560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131590 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 + 131590 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080008570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6601 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13159 +instret:6602 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13159 + 131600 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080008570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131600 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 131600 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6603 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13160 +instret:6604 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13160 + 131610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08580, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6605 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13161 +instret:6606 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13161 + 131620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080008580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6607 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13162 +instret:6608 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13162 + 131630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008580, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 131630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080008580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:6609 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13163 +instret:6610 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13163 +instret:6611 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13164 +instret:6612 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13164 +instret:6613 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13165 +instret:6614 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13165 +instret:6615 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13166 +instret:6616 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13166 +instret:6617 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13167 +instret:6618 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13167 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08590, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6619 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13168 +instret:6620 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13168 +instret:6621 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13169 +instret:6622 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13169 +instret:6623 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13170 +instret:6624 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13170 +instret:6625 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13171 +instret:6626 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13171 +instret:6627 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13172 +instret:6628 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13172 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6629 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13173 +instret:6630 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13173 +instret:6631 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13174 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 131830 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800070c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h0 } + 131840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040003, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131840 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 131840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h00000000800070c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 131840 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 131850 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080008590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131860 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 131860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080008590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 131860 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 + 132140 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008570, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 132150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132150 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 132150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008570, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 132160 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080008540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132160 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h09, addr: 'h0000000080008540, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132160 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 132160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800085a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008550, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 132180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080008560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0b, addr: 'h0000000080008560, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 132190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080008570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0c, addr: 'h0000000080008570, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132190 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6632 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13219 + 132200 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800085a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132200 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 + 132200 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800085b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132210 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800085b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132210 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 132210 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800085c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6633 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13221 +instret:6634 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13221 + 132220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800085c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6635 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13222 +instret:6636 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13222 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6637 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13223 +instret:6638 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13223 + 132240 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800085c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800085c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 132240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800085c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6639 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13224 +instret:6640 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13224 + 132250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800085c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +instret:6641 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13225 +instret:6642 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13225 +instret:6643 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13226 +instret:6644 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13226 +instret:6645 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13227 +instret:6646 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13227 +instret:6647 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13228 +instret:6648 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13228 +instret:6649 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13229 +instret:6650 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13229 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6651 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13230 +instret:6652 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13230 + 132310 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800085d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6653 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13231 +instret:6654 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13231 + 132320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800085d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132320 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h3 +instret:6655 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13232 +instret:6656 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13232 +instret:6657 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13233 +instret:6658 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13233 +instret:6659 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13234 +instret:6660 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13234 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6661 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13235 +instret:6662 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13235 +instret:6663 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13236 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe085f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 132450 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008580, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 132460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132460 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 132460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008580, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132460 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 132470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080008580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0d, addr: 'h0000000080008580, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 132470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800085e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132480 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080008590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132480 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0e, addr: 'h0000000080008590, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132480 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 132490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800085a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0f, addr: 'h00000000800085a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 132500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800085b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h10, addr: 'h00000000800085b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6664 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13250 + 132510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800085e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h2 + 132510 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800085f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132520 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800085f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132520 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h4 + 132520 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6665 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13252 +instret:6666 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13252 + 132530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6667 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13253 +instret:6668 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13253 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08600, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6669 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13254 +instret:6670 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13254 + 132550 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008600, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 132550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080008600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6671 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13255 +instret:6672 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13255 + 132560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080008600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h6 +instret:6673 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13256 +instret:6674 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13256 +instret:6675 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13257 +instret:6676 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13257 +instret:6677 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13258 +instret:6678 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13258 +instret:6679 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13259 +instret:6680 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13259 +instret:6681 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13260 +instret:6682 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13260 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08610, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6683 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13261 +instret:6684 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13261 + 132620 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080008610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6685 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13262 +instret:6686 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13262 + 132630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080008610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132630 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h7 +instret:6687 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13263 +instret:6688 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13263 +instret:6689 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13264 +instret:6690 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13264 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08620, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6691 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13265 +instret:6692 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13265 +instret:6693 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13266 +instret:6694 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13266 +instret:6695 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13267 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08630, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 132760 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800085c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 132770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132770 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 132770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800085c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132770 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 132780 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800085c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132780 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h11, addr: 'h00000000800085c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132780 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 132780 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080008620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132790 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800085d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132790 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h12, addr: 'h00000000800085d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132790 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 132800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800085e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h13, addr: 'h00000000800085e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 132810 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800085f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132810 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 132810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h14, addr: 'h00000000800085f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132810 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6696 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13281 + 132820 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080008620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132820 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h1 + 132820 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h6, depend on cRq tagged Valid 'h5 + 132830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080008640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6697 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13283 +instret:6698 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13283 + 132840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080008640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 132840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6699 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13284 +instret:6700 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13284 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08640, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6701 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13285 +instret:6702 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13285 + 132860 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080008640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008640, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 132860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080008640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6703 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13286 +instret:6704 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13286 + 132870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080008640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h2 +instret:6705 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13287 +instret:6706 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13287 +instret:6707 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13288 +instret:6708 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13288 +instret:6709 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13289 +instret:6710 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13289 +instret:6711 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13290 +instret:6712 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13290 +instret:6713 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13291 +instret:6714 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13291 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08650, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6715 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13292 +instret:6716 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13292 + 132930 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080008650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6717 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13293 +instret:6718 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13293 + 132940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 132940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080008650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 132940 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h4 +instret:6719 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13294 +instret:6720 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13294 +instret:6721 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13295 +instret:6722 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13295 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08660, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6723 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13296 +instret:6724 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13296 +instret:6725 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13297 +instret:6726 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13297 +instret:6727 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13298 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08670, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 133070 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008600, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 133080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133080 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 133080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h0a, addr: 'h0000000080008600, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133080 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 133090 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080008600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133090 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h15, addr: 'h0000000080008600, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133090 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 133090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080008660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080008610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h16, addr: 'h0000000080008610, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 133110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080008620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h17, addr: 'h0000000080008620, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133110 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 133120 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133120 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080008630, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133120 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6728 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13312 + 133130 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080008660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133130 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h0 + 133130 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080008670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133140 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080008670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133140 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h2, depend on cRq tagged Valid 'h6 + 133140 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6729 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13314 +instret:6730 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13314 + 133150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6731 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13315 +instret:6732 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13315 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08680, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6733 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13316 +instret:6734 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13316 + 133170 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008680, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 133170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080008680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6735 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13317 +instret:6736 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13317 + 133180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080008680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h1 +instret:6737 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13318 +instret:6738 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13318 +instret:6739 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13319 +instret:6740 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13319 +instret:6741 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13320 +instret:6742 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13320 +instret:6743 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13321 +instret:6744 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13321 +instret:6745 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13322 +instret:6746 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13322 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08690, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6747 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13323 +instret:6748 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13323 + 133240 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080008690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6749 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13324 +instret:6750 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13324 + 133250 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080008690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133250 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h5 +instret:6751 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13325 +instret:6752 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13325 +instret:6753 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13326 +instret:6754 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13326 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6755 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13327 +instret:6756 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13327 +instret:6757 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13328 +instret:6758 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13328 +instret:6759 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13329 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 133380 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008640, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 133390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133390 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 133390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h0000000080008640, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 133400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080008640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h01, addr: 'h0000000080008640, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 133400 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800086a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133410 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080008650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133410 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h02, addr: 'h0000000080008650, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133410 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 133420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080008660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h03, addr: 'h0000000080008660, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133420 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 133430 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080008670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133430 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h04, addr: 'h0000000080008670, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133430 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6760 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13343 + 133440 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800086a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133440 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h3 + 133440 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800086b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133450 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800086b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133450 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h1, depend on cRq tagged Valid 'h2 + 133450 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800086c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6761 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13345 +instret:6762 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13345 + 133460 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800086c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133460 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6763 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13346 +instret:6764 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13346 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6765 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13347 +instret:6766 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13347 + 133480 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800086c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h00000000800086c0, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 133480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800086c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6767 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13348 +instret:6768 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13348 + 133490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800086c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0 +instret:6769 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13349 +instret:6770 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13349 +instret:6771 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13350 +instret:6772 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13350 +instret:6773 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13351 +instret:6774 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13351 +instret:6775 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13352 +instret:6776 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13352 +instret:6777 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13353 +instret:6778 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13353 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6779 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13354 +instret:6780 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13354 + 133550 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800086d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6781 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13355 +instret:6782 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13355 + 133560 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800086d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133560 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h6 +instret:6783 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13356 +instret:6784 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13356 +instret:6785 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13357 +instret:6786 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13357 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086e0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6787 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13358 +instret:6788 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13358 +instret:6789 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13359 +instret:6790 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13359 +instret:6791 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13360 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe086f0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 133690 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008680, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 133700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133700 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 133700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0a, addr: 'h0000000080008680, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 133710 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080008680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133710 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h05, addr: 'h0000000080008680, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133710 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 133710 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800086e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133720 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080008690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133720 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h06, addr: 'h0000000080008690, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133720 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 133730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800086a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h07, addr: 'h00000000800086a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 133740 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800086b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133740 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 133740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h08, addr: 'h00000000800086b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133740 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6792 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13374 + 133750 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800086e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133750 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h7 + 133750 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800086f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133760 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800086f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133760 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h1 + 133760 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6793 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13376 +instret:6794 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13376 + 133770 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 133770 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6795 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13377 +instret:6796 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13377 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08700, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6797 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13378 +instret:6798 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13378 + 133790 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008700, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 133790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080008700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6799 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13379 +instret:6800 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13379 + 133800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080008700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h3 +instret:6801 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13380 +instret:6802 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13380 +instret:6803 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13381 +instret:6804 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13381 +instret:6805 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13382 +instret:6806 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13382 +instret:6807 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13383 +instret:6808 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13383 +instret:6809 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13384 +instret:6810 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13384 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08710, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6811 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13385 +instret:6812 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13385 + 133860 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080008710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6813 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13386 +instret:6814 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13386 + 133870 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 133870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080008710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 133870 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h2 +instret:6815 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13387 +instret:6816 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13387 +instret:6817 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13388 +instret:6818 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13388 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08720, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6819 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13389 +instret:6820 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13389 +instret:6821 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13390 +instret:6822 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13390 +instret:6823 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13391 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08730, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 134000 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h00000000800086c0, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 134010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134010 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 134010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0a, addr: 'h00000000800086c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134010 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 134020 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800086c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134020 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h00000000800086c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134020 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 134020 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080008720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134030 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800086d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134030 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h00000000800086d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134030 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 134040 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800086e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134040 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h0b, addr: 'h00000000800086e0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134040 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 134050 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800086f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134050 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0c, addr: 'h00000000800086f0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134050 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6824 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13405 + 134060 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080008720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134060 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h4 + 134060 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080008730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134070 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080008730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134070 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h3, depend on cRq tagged Valid 'h0 + 134070 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6825 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13407 +instret:6826 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13407 + 134080 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134080 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6827 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13408 +instret:6828 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13408 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08740, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6829 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13409 +instret:6830 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13409 + 134100 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008740, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 134100 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080008740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6831 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13410 +instret:6832 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13410 + 134110 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080008740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134110 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h7 +instret:6833 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13411 +instret:6834 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13411 +instret:6835 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13412 +instret:6836 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13412 +instret:6837 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13413 +instret:6838 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13413 +instret:6839 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13414 +instret:6840 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13414 +instret:6841 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13415 +instret:6842 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13415 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08750, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6843 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13416 +instret:6844 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13416 + 134170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6845 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13417 +instret:6846 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13417 + 134180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h1 +instret:6847 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13418 +instret:6848 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13418 +instret:6849 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13419 +instret:6850 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13419 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08760, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6851 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13420 +instret:6852 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13420 +instret:6853 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13421 +instret:6854 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13421 +instret:6855 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13422 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08770, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 134310 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008700, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 134320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134320 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 134320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008700, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 134330 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080008700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134330 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0d, addr: 'h0000000080008700, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134330 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h4 + 134330 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080008710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134340 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0e, addr: 'h0000000080008710, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 134350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080008720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h0f, addr: 'h0000000080008720, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 134360 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080008730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134360 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h10, addr: 'h0000000080008730, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134360 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6856 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13436 + 134370 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134370 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h5 + 134370 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080008770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080008770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134380 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h7, depend on cRq tagged Valid 'h3 + 134380 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6857 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13438 +instret:6858 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13438 + 134390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6859 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13439 +instret:6860 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13439 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08780, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6861 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13440 +instret:6862 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13440 + 134410 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008780, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 134410 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6863 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13441 +instret:6864 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13441 + 134420 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134420 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h4 +instret:6865 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13442 +instret:6866 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13442 +instret:6867 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13443 +instret:6868 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13443 +instret:6869 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13444 +instret:6870 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13444 +instret:6871 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13445 +instret:6872 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13445 +instret:6873 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13446 +instret:6874 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13446 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe08790, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6875 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13447 +instret:6876 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13447 + 134480 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080008790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6877 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13448 +instret:6878 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13448 + 134490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080008790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h0 +instret:6879 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13449 +instret:6880 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13449 +instret:6881 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13450 +instret:6882 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13450 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087a0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6883 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13451 +instret:6884 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13451 +instret:6885 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13452 +instret:6886 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13452 +instret:6887 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13453 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087b0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } + 134620 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008740, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 134630 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134630 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 134630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h0a, addr: 'h0000000080008740, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134630 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 134640 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080008740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134640 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h11, addr: 'h0000000080008740, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134640 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h5 + 134640 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h17, addr: 'h00000000800087a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134650 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h12, addr: 'h0000000080008750, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h3 + 134660 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134660 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h13, addr: 'h0000000080008760, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134660 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h2 + 134670 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h2, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080008770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134670 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h14, addr: 'h0000000080008770, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134670 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6888 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13467 + 134680 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h00000000800087a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134680 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h6 + 134680 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800087b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134690 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800087b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134690 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h4, depend on cRq tagged Valid 'h7 + 134690 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800087c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6889 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13469 +instret:6890 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13469 + 134700 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800087c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134700 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 134700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h00000000800087c0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134700 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6891 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13470 +instret:6892 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13470 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087c0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6893 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13471 +instret:6894 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13471 + 134720 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800087c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6895 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13472 +instret:6896 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13472 + 134730 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800087c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134730 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 134730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h01, addr: 'h00000000800087c0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134730 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6897 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13473 +instret:6898 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13473 +instret:6899 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13474 +instret:6900 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13474 +instret:6901 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13475 +instret:6902 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13475 +instret:6903 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13476 +instret:6904 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13476 +instret:6905 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13477 +instret:6906 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13477 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe087d0, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6907 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13478 +instret:6908 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13478 + 134790 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800087d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } +instret:6909 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13479 +instret:6910 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13479 + 134800 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800087d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134800 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 134800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h02, addr: 'h00000000800087d0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134800 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6911 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13480 +instret:6912 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13480 + 134820 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6913 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13482 +instret:6914 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13482 + 134830 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134830 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace + 134830 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6915 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13483 +instret:6916 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13483 + 134840 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134840 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace +instret:6917 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13484 +instret:6918 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13484 + 134850 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008810, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } +instret:6919 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13485 + 134860 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } ; L1CRqSlot { way: 'h2, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080008850, fromState: I, toState: S, canUpToE: True, id: 'h2, child: , isPrefetchRq: False } + 134930 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008780, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 134940 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h3 ; PRqMsg { addr: 'h00000000800028d8, toState: S, child: } + 134940 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h4, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134940 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 134940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008780, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 134940 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h0 + 134950 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h0, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134950 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h15, addr: 'h0000000080008780, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134950 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h6 + 134960 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h6, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080008790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134960 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h16, addr: 'h0000000080008790, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134960 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h7 + 134970 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h7, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h17, addr: 'h00000000800087a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134970 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h17, addr: 'h00000000800087a0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134970 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Valid 'h1 + 134980 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h1, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 134980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800087b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134980 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit + 134980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h00000000800087b0, toState: E, op: Ld, byteEn: , data: TaggedData { tag: False, data: }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'hd894 } + 134980 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +instret:6920 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [0]] 13498 + 134990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h3 ; PRqMsg { addr: 'h00000000800028d8, toState: S, child: } + 134990 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 134990 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800087d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } + 135000 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h3 ; PRqMsg { addr: 'h00000000800028d8, toState: S, child: } ; CRsMsg { addr: 'h00000000800028d8, toState: S, data: tagged Invalid , child: } + 135000 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: M, dir: , owner: tagged Invalid , other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 135000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800087d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 135000 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit + 135000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h0a, addr: 'h00000000800087d0, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 135000 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid + 135000 L1 top.soc_top.corew_proc.core_0 createPrefetchRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: , data: }, amoInst: AmoInst { func: , width: , aq: , rl: }, loadTags: , pcHash: 'haaaa } +instret:6921 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13500 +instret:6922 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13500 + 135010 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: I, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 135010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 135010 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h5, depend on cRq tagged Valid 'h5 +instret:6923 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13501 +instret:6924 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13501 +instret:6925 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13502 +instret:6926 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13502 +instret:6927 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13503 +instret:6928 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13503 +instret:6929 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13504 +instret:6930 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13504 +instret:6931 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13505 +instret:6932 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13505 +instret:6933 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13506 +instret:6934 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13506 +instret:6935 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13507 +instret:6936 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13507 +instret:6937 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13508 +instret:6938 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13508 +instret:6939 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13509 +instret:6940 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13509 +instret:6941 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13510 +instret:6942 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13510 +instret:6943 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13511 +instret:6944 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13511 +instret:6945 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13512 +instret:6946 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13512 +instret:6947 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13513 +instret:6948 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13513 +instret:6949 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13514 +instret:6950 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13514 +instret:6951 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13515 +instret:6952 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13515 +instret:6953 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13516 +instret:6954 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13516 +instret:6955 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13517 +instret:6956 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13517 +instret:6957 PC:0x1ffff000000000000ffffffffffe02768 instr:0x00cc5793 iType:Alu [doCommitNormalInst [0]] 13518 +instret:6958 PC:0x1ffff000000000000ffffffffffe0276c instr:0x00479413 iType:Alu [doCommitNormalInst [1]] 13518 +instret:6959 PC:0x1ffff000000000000ffffffffffe02770 instr:0x00848733 iType:Alu [doCommitNormalInst [0]] 13519 +instret:6960 PC:0x1ffff000000000000ffffffffffe02774 instr:0x00073703 iType:Ld [doCommitNormalInst [1]] 13519 + 135200 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h0 ; PRqMsg { addr: 'h0000000080002234, toState: S, child: } +instret:6961 PC:0x1ffff000000000000ffffffffffe02778 instr:0xfe0702e3 iType:Br [doCommitNormalInst [0]] 13520 +instret:6962 PC:0x1ffff000000000000ffffffffffe0275c instr:0x000017b7 iType:Alu [doCommitNormalInst [1]] 13520 + 135210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h0 ; PRqMsg { addr: 'h0000000080002234, toState: S, child: } + 135210 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process +instret:6963 PC:0x1ffff000000000000ffffffffffe02760 instr:0x00fc0c33 iType:Alu [doCommitNormalInst [0]] 13521 +instret:6964 PC:0x1ffff000000000000ffffffffffe02764 instr:0x173c0a63 iType:Br [doCommitNormalInst [1]] 13521 + 135220 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h0 ; PRqMsg { addr: 'h0000000080002234, toState: S, child: } ; CRsMsg { addr: 'h0000000080002234, toState: S, data: tagged Invalid , child: } +instret:6965 PC:0x1ffff000000000000ffffffffffe028d8 instr:0x00090513 iType:Alu [doCommitNormalInst [0]] 13522 +instret:6966 PC:0x1ffff000000000000ffffffffffe028dc instr:0x959ff0ef iType:J [doCommitNormalInst [1]] 13522 + 135330 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008810, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 135340 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h5, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 135340 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 135340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h0a, addr: 'h0000000080008810, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 135340 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe01000, write: False, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excLoadPageFault, allowCap: False } +instret:6967 PC:0x1ffff000000000000ffffffffffe02234 instr:0xfffff797 iType:Auipc [doCommitNormalInst [0]] 13537 +instret:6968 PC:0x1ffff000000000000ffffffffffe02238 instr:0xdcc78793 iType:Alu [doCommitNormalInst [0]] 13538 + 135410 L1 top.soc_top.corew_proc.core_0 pRqTransfer: 'h1 ; PRqMsg { addr: 'h0000000080002240, toState: S, child: } + 135420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: 'h1 ; PRqMsg { addr: 'h0000000080002240, toState: S, child: } + 135420 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRq: valid process + 135430 L1 top.soc_top.corew_proc.core_0 sendRsToP: tagged PRq 'h1 ; PRqMsg { addr: 'h0000000080002240, toState: S, child: } ; CRsMsg { addr: 'h0000000080002240, toState: S, data: tagged Invalid , child: } +instret:6969 PC:0x1ffff000000000000ffffffffffe0223c instr:0x0007b703 iType:Ld [doCommitNormalInst [0]] 13546 +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe01040, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:6970 PC:0x1ffff000000000000ffffffffffe02240 instr:0x00070a63 iType:Br [doCommitNormalInst [0]] 13559 + 135640 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080008850, toState: E, child: , data: tagged Valid CLine { tag: , data: > }, id: 'h2 } + 135650 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h2, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040004, cs: E, dir: , owner: tagged Valid 'h3, other: }, line: CLine { tag: , data: > } }, repInfo: , setAuxData: tagged Invalid } + 135650 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: + 135650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h0a, addr: 'h0000000080008850, toState: S, op: Ld, byteEn: , data: TaggedData { tag: True, data: }, amoInst: AmoInst { func: Min, width: DWord, aq: False, rl: True }, loadTags: False, pcHash: 'haaaa } + 135650 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: , data: > } ; tagged Invalid +procReq: vm_info: VMInfo { prv: 'h1, asid: 'h0, sv39: True, exeReadable: False, userAccessibleByS: False, basePPN: 'h00000080004, globalCapLoadGenU: 'h0, globalCapLoadGenS: 'h0 } en : TlbEntry { vpn: 'h7fffe00, ppn: 'h00000080000, pteType: PTEType { dirty: True, accessed: True, global: False, user: False, executable: True, writable: True, readable: True }, pteUpperType: PTEUpperType { cap_writable: False, cap_readable: False, cap_dirty: False, cap_read_mod: False, cap_read_gen: False }, level: 'h1, asid: 'h0 } r : TlbReq { addr: 'hffffffffffe01000, write: True, capStore: False, potentialCapLoad: False } +Permission check output 2: TlbPermissionCheck { allowed: True, excCode: excStorePageFault, allowCap: False } +instret:6971 PC:0x1ffff000000000000ffffffffffe02254 instr:0xfffff797 iType:Auipc [doCommitNormalInst [0]] 13567 +13573: mmioPlatform.rl_tohost: 0x1 (= 1) +PASS diff --git a/src_Core/CPU/MMIOPlatform.bsv b/src_Core/CPU/MMIOPlatform.bsv index 6a7f7d1..1c38673 100644 --- a/src_Core/CPU/MMIOPlatform.bsv +++ b/src_Core/CPU/MMIOPlatform.bsv @@ -921,11 +921,11 @@ module mkMMIOPlatform #(Vector#(CoreNum, MMIOCoreToPlatform) cores, // Stay in WaitResp but wait to discard the write response amoWaitWriteResp <= True; - if (verbosity > 1) begin - $display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d", - addr, reqSz, reqAmofunc); - $display (" ld_val 0x%0h op st_val 0x%0h => new_st_val 0x%0h", ld_val, reqData, new_st_val); - end + // if (verbosity > 1) begin + $display ("MMIO_Platform.rl_mmio_from_fabric_amo_rsp: addr 0x%0h, size %0d, amofunc %0d", + addr, reqSz, reqAmofunc); + $display (" ld_val 0x%0h op st_val 0x%0h => new_st_val 0x%0h", ld_val, reqData, new_st_val); + // end end endrule diff --git a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv index 410323d..9155d61 100644 --- a/src_Core/Core/Trace_Data2_to_Trace_Data.bsv +++ b/src_Core/Core/Trace_Data2_to_Trace_Data.bsv @@ -244,10 +244,10 @@ module mkTrace_Data2_to_Trace_Data (Trace_Data2_to_Trace_Data_IFC); rule rl_td2_to_td; Trace_Data2 td2 <- pop (f_in); - if (verbosity > 1) - $display ("%0d: %m.rl_td2_to_td: serial_num:%0d PC:0x%0h instr:0x%08h", - cur_cycle, td2.serial_num, td2.pc, td2.orig_inst, - " iType:", fshow (td2.iType)); + // if (verbosity > 1) + $display ("%0d: %m.rl_td2_to_td: serial_num:%0d PC:0x%0h instr:0x%08h", + cur_cycle, td2.serial_num, td2.pc, td2.orig_inst, + " iType:", fshow (td2.iType)); match { .serial_num, .td } <- fav_td2_to_td (td2); f_out.enq (tuple2 (serial_num, td));