From 2918854bbc446e578393605c883ca7c1845d0971 Mon Sep 17 00:00:00 2001
From: jon <jonwoodruff@gmail.com>
Date: Tue, 7 Apr 2020 12:37:14 +0100
Subject: [PATCH] Add missing ifdef.

---
 src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
index 060cf26..2d19493 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv
@@ -243,7 +243,9 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline);
         end
         // update the instruction in the reorder buffer.
         inIfc.rob_setExecuted(tag, data, fflags, tagged Invalid, cast(inIfc.scaprf_rd(SCR_PCC))
+`ifdef RVFI_DII
                               , ExtraTraceBundle{regWriteData: data, memByteEn: ?}
+`endif
         );
         // since FPU op has no spec tag, this doFinish rule is ordered before
         // other rules that calls incorrectSpec, and BSV compiler creates