diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
index 344cd26..b436b89 100644
--- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv
@@ -1352,7 +1352,7 @@ provisos(
 endmodule
 
 typedef enum {
-  EMPTY = 3'd0, INIT = 3'd1, TRANSIENT = 3'd2, STEADY = 3'd3, NO_PRED = 3'd4
+  INIT = 2'd0, TRANSIENT = 2'd1, STEADY = 2'd2, NO_PRED = 2'd3
 } StrideState2 deriving (Bits, Eq, FShow);
 
 typedef struct {
@@ -1402,17 +1402,7 @@ provisos(
         $writeh("%t Stride Prefetcher updateStrideEntry ", $time,
             fshow(hitMiss), " ", addr,
             ". Entry ", index, " state is ", fshow(se.state));
-        if (se.state == EMPTY) begin
-            if (hitMiss == MISS) begin 
-                seNext.lastAddr = truncate(addr);
-                seNext.state = INIT;
-                $display(", allocate entry");
-            end
-            else begin
-                $display(", ignore");
-            end
-        end 
-        else if (se.state == INIT && observedStride != 0) begin
+        if (se.state == INIT && observedStride != 0) begin
             if (se.stride == observedStride) begin
                 //fast track to steady
                 seNext.state = STEADY;
diff --git a/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv b/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv
index 4fd3d1f..0570eb4 100644
--- a/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv
@@ -952,7 +952,11 @@ module mkStride2PCPrefetcherTest(Empty);
             action p.reportAccess('h90000160, 'h006a, HIT); endaction
             action
                 let x <- p.getNextPrefetchAddr;
-                doAssert(x == 'h90000120, "test fail!");
+                doAssert(x == 'h90000150, "test fail!");
+            endaction
+            action
+                let x <- p.getNextPrefetchAddr;
+                doAssert(x == 'h90000110, "test fail!");
             endaction
             action
                 let x <- p.getNextPrefetchAddr;
@@ -961,14 +965,13 @@ module mkStride2PCPrefetcherTest(Empty);
             action p.reportAccess('h90000100, 'h006b, MISS); endaction
             action p.reportAccess('h90000200, 'h006b, MISS); endaction
             action p.reportAccess('h90000300, 'h006b, MISS); endaction
-            action p.reportAccess('h90000400, 'h006b, MISS); endaction
             action
                 let x <- p.getNextPrefetchAddr;
-                doAssert(x == 'h90000500, "test fail!");
+                doAssert(x == 'h90000400, "test fail!");
             endaction
             action
                 let x <- p.getNextPrefetchAddr;
-                doAssert(x == 'h90000600, "test fail!");
+                doAssert(x == 'h90000500, "test fail!");
             endaction
             action p.reportAccess('ha0000420, 'h006b, MISS); endaction
             action p.reportAccess('ha0000520, 'h006b, MISS); endaction