From 2f428a974a7bdafa2a19d1c0036bb7a8efa40961 Mon Sep 17 00:00:00 2001 From: Karlis Susters Date: Thu, 13 Apr 2023 18:27:28 +0300 Subject: [PATCH] Reduce bit storage for stride prefetcher --- src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index b436b89..f4d517f 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -1358,7 +1358,7 @@ typedef enum { typedef struct { Bit#(12) lastAddr; Bit#(13) stride; - Bit#(4) cLinesPrefetched; //Stores how many cache lines have been prefetched for this instruction + Bit#(2) cLinesPrefetched; //Stores how many cache lines have been prefetched for this instruction StrideState2 state; } StrideEntry2 deriving (Bits, Eq, FShow); @@ -1374,7 +1374,7 @@ provisos( Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo; FIFO#(Tuple3#(StrideEntry2, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO(); - Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?); + Reg#(Maybe#(Bit#(2))) cLinesPrefetchedLatest <- mkReg(?); PulseWire holdReadReq <- mkPulseWire; rule sendReadReq if (!holdReadReq); @@ -1467,7 +1467,7 @@ provisos( rule createPrefetchRequests; match {.se, .addr, .pcHash} = strideEntryForPrefetch.first; //If this rule is looping, then we'll have a valid cLinesPrefetchedLatest - Bit#(4) cLinesPrefetched = fromMaybe(se.cLinesPrefetched, cLinesPrefetchedLatest); + Bit#(2) cLinesPrefetched = fromMaybe(se.cLinesPrefetched, cLinesPrefetchedLatest); if (se.state == STEADY && cLinesPrefetched !=