diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv
index e310ece..5152fef 100644
--- a/src_Core/CPU/Proc.bsv
+++ b/src_Core/CPU/Proc.bsv
@@ -237,91 +237,6 @@ module mkProc (Proc_IFC);
       endrule
    end
 
-/*
-   // ================================================================
-   // Send and print perf requests 
-
-   Reg#(Bit#(4)) perfCnt <- mkReg(0);
-   Reg#(Bool) requestSent <- mkReg(False);
-   rule rl_sendLLCPerfReq if (!requestSent);
-      perfCnt <= (perfCnt == 12) ? 0 : perfCnt + 1;
-      case (perfCnt)
-         'b1001: llc.perf.req(LLCNormalMemLdCnt);
-         'b1010: llc.perf.req(LLCNormalMemLdLat);
-         'b1011: llc.perf.req(LLCInstructionLdCnt);
-         'b1100: llc.perf.req(LLCInstructionLdLat);
-      endcase
-      requestSent <= True;
-   endrule
-   rule rl_printLLCPerfResp;
-      let perfResp <- llc.perf.resp;
-      requestSent <= False;
-      if (perfResp.pType == LLCNormalMemLdCnt) begin
-         $display("%0d: LLC data miss count: %d", cur_cycle, unpack(perfResp.data));
-      end
-      else if (perfResp.pType == LLCNormalMemLdLat) begin
-         $display("%0d: LLC data miss latency: %d", cur_cycle, unpack(perfResp.data));
-      end
-      else if (perfResp.pType == LLCInstructionLdCnt) begin
-         $display("%0d: LLC instruction miss count: %d", cur_cycle, unpack(perfResp.data));
-      end
-      else if (perfResp.pType == LLCInstructionLdLat) begin
-         $display("%0d: LLC instruction miss latency: %d", cur_cycle, unpack(perfResp.data));
-      end
-   endrule
-
-   for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin
-      rule rl_sendPerfReq if (!requestSent);
-         case (perfCnt)
-            'b0000: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdCnt)));
-            'b0001: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdMissCnt)));
-            'b0010: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdMissLat)));
-            'b0011: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdCnt)));
-            'b0100: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdMissCnt)));
-            'b0101: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdMissLat)));
-            'b0110: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStCnt)));
-            'b0111: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStMissCnt)));
-            'b1000: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStMissLat)));
-         endcase
-      endrule
-
-      rule rl_printPerfResp;
-         let perfResp <- core[i].coreIndInv.perfResp;
-         requestSent <= False;
-         if (perfResp.loc == ICache) begin
-            if (perfResp.pType == zeroExtend(pack(L1ILdCnt))) begin
-               $display("%0d: L1I load count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1ILdMissCnt))) begin
-               $display("%0d: L1I load miss count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1ILdMissLat))) begin
-               $display("%0d: L1I load miss latency: %d", cur_cycle, unpack(perfResp.data));
-            end
-         end
-         else if (perfResp.loc == DCache) begin 
-            if (perfResp.pType == zeroExtend(pack(L1DLdCnt))) begin
-               $display("%0d: L1D load count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1DLdMissCnt))) begin
-               $display("%0d: L1D load miss count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1DLdMissLat))) begin
-               $display("%0d: L1D load miss latency: %d", cur_cycle, unpack(perfResp.data));
-            end
-            if (perfResp.pType == zeroExtend(pack(L1DStCnt))) begin
-               $display("%0d: L1D store count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1DStMissCnt))) begin
-               $display("%0d: L1D store miss count: %d", cur_cycle, unpack(perfResp.data));
-            end
-            else if (perfResp.pType == zeroExtend(pack(L1DStMissLat))) begin
-               $display("%0d: L1D store miss latency: %d", cur_cycle, unpack(perfResp.data));
-            end
-         end
-      endrule
-   end
-*/
 
    // ================================================================
    // Print out values written 'tohost'
diff --git a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
index 9826548..856fb1d 100644
--- a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv
@@ -97,7 +97,7 @@ module mkRWBramCoreForwarded(RWBramCore#(addrT, dataT)) provisos(
 
     method Action rdReq(addrT a);
         if (currentWriteAddr.wget matches tagged Valid .writeAddr &&& writeAddr == a) begin
-            $display ("%t Write same addr as read -- forwarding data!", $time);
+            //$display ("%t Write same addr as read -- forwarding data!", $time);
             rdReqQ.enq(Valid(fromMaybe(?, currentWriteData.wget)));
         end
         else begin