diff --git a/src_Core/CPU/Proc.bsv b/src_Core/CPU/Proc.bsv index e310ece..5152fef 100644 --- a/src_Core/CPU/Proc.bsv +++ b/src_Core/CPU/Proc.bsv @@ -237,91 +237,6 @@ module mkProc (Proc_IFC); endrule end -/* - // ================================================================ - // Send and print perf requests - - Reg#(Bit#(4)) perfCnt <- mkReg(0); - Reg#(Bool) requestSent <- mkReg(False); - rule rl_sendLLCPerfReq if (!requestSent); - perfCnt <= (perfCnt == 12) ? 0 : perfCnt + 1; - case (perfCnt) - 'b1001: llc.perf.req(LLCNormalMemLdCnt); - 'b1010: llc.perf.req(LLCNormalMemLdLat); - 'b1011: llc.perf.req(LLCInstructionLdCnt); - 'b1100: llc.perf.req(LLCInstructionLdLat); - endcase - requestSent <= True; - endrule - rule rl_printLLCPerfResp; - let perfResp <- llc.perf.resp; - requestSent <= False; - if (perfResp.pType == LLCNormalMemLdCnt) begin - $display("%0d: LLC data miss count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == LLCNormalMemLdLat) begin - $display("%0d: LLC data miss latency: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == LLCInstructionLdCnt) begin - $display("%0d: LLC instruction miss count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == LLCInstructionLdLat) begin - $display("%0d: LLC instruction miss latency: %d", cur_cycle, unpack(perfResp.data)); - end - endrule - - for(Integer i = 0; i < valueof(CoreNum); i = i+1) begin - rule rl_sendPerfReq if (!requestSent); - case (perfCnt) - 'b0000: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdCnt))); - 'b0001: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdMissCnt))); - 'b0010: core[i].coreReq.perfReq(ICache, zeroExtend(pack(L1ILdMissLat))); - 'b0011: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdCnt))); - 'b0100: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdMissCnt))); - 'b0101: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DLdMissLat))); - 'b0110: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStCnt))); - 'b0111: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStMissCnt))); - 'b1000: core[i].coreReq.perfReq(DCache, zeroExtend(pack(L1DStMissLat))); - endcase - endrule - - rule rl_printPerfResp; - let perfResp <- core[i].coreIndInv.perfResp; - requestSent <= False; - if (perfResp.loc == ICache) begin - if (perfResp.pType == zeroExtend(pack(L1ILdCnt))) begin - $display("%0d: L1I load count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1ILdMissCnt))) begin - $display("%0d: L1I load miss count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1ILdMissLat))) begin - $display("%0d: L1I load miss latency: %d", cur_cycle, unpack(perfResp.data)); - end - end - else if (perfResp.loc == DCache) begin - if (perfResp.pType == zeroExtend(pack(L1DLdCnt))) begin - $display("%0d: L1D load count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1DLdMissCnt))) begin - $display("%0d: L1D load miss count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1DLdMissLat))) begin - $display("%0d: L1D load miss latency: %d", cur_cycle, unpack(perfResp.data)); - end - if (perfResp.pType == zeroExtend(pack(L1DStCnt))) begin - $display("%0d: L1D store count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1DStMissCnt))) begin - $display("%0d: L1D store miss count: %d", cur_cycle, unpack(perfResp.data)); - end - else if (perfResp.pType == zeroExtend(pack(L1DStMissLat))) begin - $display("%0d: L1D store miss latency: %d", cur_cycle, unpack(perfResp.data)); - end - end - endrule - end -*/ // ================================================================ // Print out values written 'tohost' diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv index 44b60d3..4ce0636 100644 --- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv @@ -12,6 +12,8 @@ // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). //- +// Prefetcher modifications: +// Copyright (c) 2023 Karlis Susters // // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation diff --git a/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv b/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv index 7db5c5a..2e5d398 100644 --- a/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv +++ b/src_Core/RISCY_OOO/coherence/src/ICRqMshr.bsv @@ -13,6 +13,8 @@ // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). //- +// Prefetcher modifications: +// Copyright (c) 2023 Karlis Susters // // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv index 2bb5045..1d20eb0 100644 --- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv @@ -13,6 +13,8 @@ // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). //- +// Prefetcher modifications: +// Copyright (c) 2023 Karlis Susters // // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation @@ -156,7 +158,7 @@ module mkL1Bank#( Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz) ); - Bool verbose = True; + Bool verbose = False; L1CRqMshr#(cRqNum, wayT, tagT, procRqT) cRqMshr <- mkL1CRqMshrLocal; @@ -191,15 +193,6 @@ module mkL1Bank#( let prefetcher <- mkL1DPrefetcher; let llcPrefetcher <- mkLLDPrefetcherInL1D; - Count#(Bit#(8)) addedCRqs <- mkCount(0); - Count#(Bit#(8)) removedCRqs <- mkCount(0); - - Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0); - Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0); - - Count#(Bit#(64)) sentPrefetchReq <- mkCount(0); - Reg#(Bit#(64)) lastReportedSentPrefetchReq <- mkReg(0); - // security flush `ifdef SECURITY_CACHES Reg#(Bool) flushDone <- mkReg(True); @@ -242,12 +235,9 @@ action `endif `ifdef PERFORMANCE_MONITORING EventsL1D events = unpack (0); - events.evt_ST = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles); - lastReportedFullCacheCycles <= currentFullCacheCycles; - $display("Reporting full cache cycles: %d", events.evt_ST); case(op) Ld: events.evt_LD = 1; - //St: events.evt_ST = 1; + St: events.evt_ST = 1; Lr, Sc, Amo: events.evt_AMO = 1; endcase perf_events[0] <= events; @@ -279,9 +269,6 @@ action `endif `ifdef PERFORMANCE_MONITORING EventsL1D events = unpack (0); - events.evt_ST_MISS = saturating_truncate(sentPrefetchReq - lastReportedSentPrefetchReq); - lastReportedSentPrefetchReq <= sentPrefetchReq; - $display("Reporting sent prefetch req: %d", events.evt_ST_MISS); case(op) Ld: begin events.evt_LD_MISS_LAT = saturating_truncate(lat); @@ -289,7 +276,7 @@ action end St: begin events.evt_ST_MISS_LAT = saturating_truncate(lat); - //events.evt_ST_MISS = 1; + events.evt_ST_MISS = 1; end Lr, Sc, Amo: begin events.evt_AMO_MISS_LAT = saturating_truncate(lat); @@ -320,7 +307,6 @@ endfunction mshrIdx: n })); cRqIsPrefetch[n] <= False; - addedCRqs.incr(1); if (verbose) $display("%t L1 %m cRqTransfer_retry: ", $time, fshow(n), " ; ", @@ -334,7 +320,6 @@ endfunction rule cRqTransfer_new(!cRqRetryIndexQ.notEmpty && flushDone); procRqT r <- toGet(rqFromCQ).get; cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r); - addedCRqs.incr(1); // send to pipeline pipeline.send(CRq (L1PipeRqIn { addr: r.addr, @@ -380,19 +365,10 @@ endfunction endrule - rule print_cRqIndexQ_len; - //$display("L1D cRqIndexQ length= %d", addedCRqs-removedCRqs); - endrule - - rule incrFullCacheCycles (addedCRqs - removedCRqs == 8); - currentFullCacheCycles.incr(1); - endrule - (* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *) (* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *) - rule createPrefetchRq(flushDone && addedCRqs - removedCRqs < 6); + rule createPrefetchRq(flushDone); Addr addr <- prefetcher.getNextPrefetchAddr; - sentPrefetchReq.incr(1); procRqT r = ProcRq { id: ?, //Or maybe do 0 here addr: addr, @@ -405,7 +381,6 @@ endfunction pcHash: ? }; cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r); - addedCRqs.incr(1); // send to pipeline pipeline.send(CRq (L1PipeRqIn { addr: r.addr, @@ -676,7 +651,6 @@ endfunction ); // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); - removedCRqs.incr(1); end else begin processAmo <= Valid (AmoHitInfo { @@ -739,7 +713,6 @@ endfunction ); // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); - removedCRqs.incr(1); // reset state processAmo <= Invalid; endrule @@ -781,7 +754,6 @@ endfunction end // release MSHR entry cRqMshr.pipelineResp.releaseEntry(n); - removedCRqs.incr(1); if (verbose) $display("%t L1 %m pipelineResp: Sc early fail func: ", $time, fshow(resetOwner), " ; ", diff --git a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv index 6ae40d8..10690ef 100644 --- a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv +++ b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv @@ -13,6 +13,8 @@ // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). //- +// Prefetcher modifications: +// Copyright (c) 2023 Karlis Susters // // Permission is hereby granted, free of charge, to any person // obtaining a copy of this software and associated documentation diff --git a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv index 587f385..ffd18c7 100644 --- a/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv +++ b/src_Core/RISCY_OOO/coherence/src/Prefetcher.bsv @@ -1,3 +1,25 @@ +// Copyright (c) 2023 Karlis Susters +// +// Permission is hereby granted, free of charge, to any person +// obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without +// restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies +// of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + import ISA_Decls :: *; import CrossBar::*; import GetPut::*; @@ -1213,17 +1235,16 @@ typedef struct { module mkBRAMStridePCPrefetcher(PCPrefetcher) provisos( NumAlias#(strideTableSize, 512), - NumAlias#(cLinesAheadToPrefetch, 2), // TODO fetch more if have repeatedly hit an entry, and if stride big + NumAlias#(cLinesAheadToPrefetch, 2), Alias#(strideTableIndexT, Bit#(TLog#(strideTableSize))) ); - //Vector#(strideTableSize, Reg#(StrideEntry)) strideTable <- replicateM(mkReg(unpack(0))); RWBramCore#(strideTableIndexT, StrideEntry) strideTable <- mkRWBramCoreForwarded; FIFOF#(Tuple3#(Addr, Bit#(16), HitOrMiss)) memAccesses <- mkSizedBypassFIFOF(8); Reg#(Tuple3#(Addr, Bit#(16), HitOrMiss)) rdRespEntry <- mkReg(?); Fifo#(8, Addr) addrToPrefetch <- mkOverflowPipelineFifo; FIFO#(Tuple3#(StrideEntry, Addr, Bit#(16))) strideEntryForPrefetch <- mkBypassFIFO(); - Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(?); + Reg#(Maybe#(Bit#(4))) cLinesPrefetchedLatest <- mkReg(Invalid); PulseWire holdReadReq <- mkPulseWire; rule sendReadReq if (!holdReadReq); @@ -1950,9 +1971,9 @@ module mkLLDPrefetcher(Prefetcher); `ifdef DATA_PREFETCHER_BLOCK let m <- mkBlockPrefetcher; `elsif DATA_PREFETCHER_STRIDE - doAssert(False, "Illegal data prefetcher type for LL cache!") - `elsif DATA_PREFETCHER_STRIDE - doAssert(False, "Illegal data prefetcher type for LL cache!") + doAssert(False, "Illegal data prefetcher type for LL cache!"); + `elsif DATA_PREFETCHER_STRIDE_ADAPTIVE + doAssert(False, "Illegal data prefetcher type for LL cache!"); `elsif DATA_PREFETCHER_MARKOV let m <- mkBRAMMarkovPrefetcher; `elsif DATA_PREFETCHER_MARKOV_ON_HIT diff --git a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv index 9826548..856fb1d 100644 --- a/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv +++ b/src_Core/RISCY_OOO/coherence/src/RWBramCore.bsv @@ -97,7 +97,7 @@ module mkRWBramCoreForwarded(RWBramCore#(addrT, dataT)) provisos( method Action rdReq(addrT a); if (currentWriteAddr.wget matches tagged Valid .writeAddr &&& writeAddr == a) begin - $display ("%t Write same addr as read -- forwarding data!", $time); + //$display ("%t Write same addr as read -- forwarding data!", $time); rdReqQ.enq(Valid(fromMaybe(?, currentWriteData.wget))); end else begin diff --git a/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv b/src_Testbench/Unit/Prefetcher_test.bsv similarity index 96% rename from src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv rename to src_Testbench/Unit/Prefetcher_test.bsv index 0ac6ef2..b5562f2 100644 --- a/src_Core/RISCY_OOO/coherence/src/test/Prefetcher_test.bsv +++ b/src_Testbench/Unit/Prefetcher_test.bsv @@ -1,3 +1,25 @@ +// Copyright (c) 2023 Karlis Susters +// +// Permission is hereby granted, free of charge, to any person +// obtaining a copy of this software and associated documentation +// files (the "Software"), to deal in the Software without +// restriction, including without limitation the rights to use, copy, +// modify, merge, publish, distribute, sublicense, and/or sell copies +// of the Software, and to permit persons to whom the Software is +// furnished to do so, subject to the following conditions: +// +// The above copyright notice and this permission notice shall be +// included in all copies or substantial portions of the Software. +// +// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +// NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +// ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +// CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +// SOFTWARE. + import Prefetcher::*; import RWBramCore::*; import StmtFSM::*; @@ -453,23 +475,26 @@ module mkBRAMSingleWindowTargetPrefetcherTest(Empty); action p.reportAccess('h80000140, MISS); //Report miss back home endaction - action - let x <- p.getNextPrefetchAddr; - doAssert(x == 'h80000180, "test fail!"); // window addresss recommended - endaction action let x <- p.getNextPrefetchAddr; //target address recommended doAssert(x == 'h81000200, "test fail!"); endaction + action + let x <- p.getNextPrefetchAddr; + doAssert(x == 'h80000180, "test fail!"); // window addresss recommended + endaction action p.reportAccess('h80000140, HIT); //Report miss back home endaction action p.reportAccess('h81000200, HIT); endaction + action + p.reportAccess('h80000140, HIT); //overwrite last target entry + endaction action let x <- p.getNextPrefetchAddr; //target addresss recommended - doAssert(x == 'h800001c0, "test fail!"); + doAssert(x == 'h81000200, "test fail!"); endaction endseq );