From 3322d1d3d778f63ad9124bac228d1380a84b4199 Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jdw57@cam.ac.uk>
Date: Thu, 16 Dec 2021 12:10:50 +0000
Subject: [PATCH] Revert "An attempt at wiring up the specUpdate interface for
 the Btb."

This reverts commit 022df36199054dcc6e8d7f3f3b1a4273fff857ad.
---
 src_Core/CPU/Core.bsv                             |  6 ++----
 src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 13 -------------
 src_Core/RISCY_OOO/procs/lib/Btb.bsv              |  4 ----
 3 files changed, 2 insertions(+), 21 deletions(-)

diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index e5be638..70f0e23 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -353,11 +353,9 @@ module mkCore#(CoreId coreId)(Core);
         end
         GlobalSpecUpdate#(CorrectSpecPortNum, ConflictWrongSpecPortNum) globalSpecUpdate <- mkGlobalSpecUpdate(
             joinSpeculationUpdate(
-                append(append(append(vec(fetchStage.specUpdate,
-                                         regRenamingTable.specUpdate,
+                append(append(append(vec(regRenamingTable.specUpdate,
                                          specTagManager.specUpdate,
-                                         fix.memExeIfc.specUpdate),
-                aluSpecUpdate), btqSpecUpdate), fpuMulDivSpecUpdate)
+                                         fix.memExeIfc.specUpdate), aluSpecUpdate), fpuMulDivSpecUpdate), btqSpecUpdate)
             ),
             rob.specUpdate
         );
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
index 8c2567c..d5383e0 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv
@@ -57,7 +57,6 @@ import CCTypes::*;
 import DefaultValue::*;
 import Ras::*;
 import EpochManager::*;
-import HasSpecBits::*;
 import Performance::*;
 import Vector::*;
 import Assert::*;
@@ -156,9 +155,6 @@ interface FetchStage;
 
     // performance
     interface Perf#(DecStagePerfType) perf;
-
-    // speculation update
-    interface SpeculationUpdate specUpdate;
 `ifdef PERFORMANCE_MONITORING
     method Bool redirect_evt;
 `endif
@@ -1019,15 +1015,6 @@ module mkFetchStage(FetchStage);
 `endif
     endinterface
 
-    interface SpeculationUpdate specUpdate;
-        method Action correctSpeculation(SpecBits sb);
-            nextAddrPred.specUpdate.correctSpeculation(sb);
-        endmethod
-        method Action incorrectSpeculation(Bool kill_all, SpecTag specTag);
-            nextAddrPred.specUpdate.incorrectSpeculation(kill_all, specTag);
-        endmethod
-    endinterface
-
 `ifdef PERFORMANCE_MONITORING
     method Bool redirect_evt = redirect_evt_reg._read;
 `endif
diff --git a/src_Core/RISCY_OOO/procs/lib/Btb.bsv b/src_Core/RISCY_OOO/procs/lib/Btb.bsv
index 7d6c792..a245fb2 100644
--- a/src_Core/RISCY_OOO/procs/lib/Btb.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Btb.bsv
@@ -43,7 +43,6 @@ import Vector::*;
 import CHERICC_Fat::*;
 import CHERICap::*;
 import SpecFifo::*;
-import HasSpecBits::*;
 
 export NextAddrPred(..);
 export mkBtb;
@@ -52,7 +51,6 @@ interface NextAddrPred#(numeric type hashSz);
     method Action put_pc(CapMem pc);
     interface Vector#(SupSizeX2, Maybe#(CapMem)) pred;
     method Action update(CapMem pc, CapMem brTarget, Bool taken, SpecBits specBits);
-    interface SpeculationUpdate specUpdate;
     // security
     method Action flush;
     method Bool flush_done;
@@ -171,8 +169,6 @@ module mkBtbCore(NextAddrPred#(hashSz))
         updateQ.enq(ToSpecFifo {spec_bits: specBits, data: BtbUpdate {pc: pc, nextPc: nextPc, taken: taken}});
     endmethod
 
-    interface SpeculationUpdate specUpdate = updateQ.specUpdate;
-
 `ifdef SECURITY
     method Action flush method Action flush;
         for (Integer i = 0; i < valueOf(SupSizeX2); i = i + 1) begin