From 34c4e0f2fa2a1eb0b981e0e5440f8c8c11993846 Mon Sep 17 00:00:00 2001 From: Peter Rugg Date: Thu, 16 Apr 2020 20:43:44 +0100 Subject: [PATCH] Comment out user exception delegation SCRs since the corresponding CSRs are not yet supported --- src_Core/CHERI/ScrFile.bsv | 16 ++++++++-------- src_Core/ISA/ISA_Decls_CHERI.bsv | 8 ++++---- 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src_Core/CHERI/ScrFile.bsv b/src_Core/CHERI/ScrFile.bsv index 54e3580..36a3c74 100644 --- a/src_Core/CHERI/ScrFile.bsv +++ b/src_Core/CHERI/ScrFile.bsv @@ -140,10 +140,10 @@ module mkScrFile (ScrFile); Reg#(CapReg) ddc_reg <- mkCsrReg(defaultValue); // User level SCRs with accessSysRegs - Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue); - Reg#(CapReg) utdc_reg <- mkCsrReg(nullCap); - Reg#(CapReg) uScratchC_reg <- mkCsrReg(nullCap); - Reg#(CapReg) uepcc_reg <- mkCsrReg(defaultValue); + // Reg#(CapReg) utcc_reg <- mkCsrReg(defaultValue); + // Reg#(CapReg) utdc_reg <- mkCsrReg(nullCap); + // Reg#(CapReg) uScratchC_reg <- mkCsrReg(nullCap); + // Reg#(CapReg) uepcc_reg <- mkCsrReg(defaultValue); // System level SCRs with accessSysRegs Reg#(CapReg) stcc_reg <- mkCsrReg(defaultValue); @@ -164,10 +164,10 @@ module mkScrFile (ScrFile); SCR_PCC: pcc_reg[0]; SCR_DDC: ddc_reg; // User CSRs with accessSysRegs - SCR_UTCC: utcc_reg; - SCR_UTDC: utdc_reg; - SCR_UScratchC: uScratchC_reg; - SCR_UEPCC: uepcc_reg; + // SCR_UTCC: utcc_reg; + // SCR_UTDC: utdc_reg; + // SCR_UScratchC: uScratchC_reg; + // SCR_UEPCC: uepcc_reg; // System CSRs with accessSysRegs SCR_STCC: stcc_reg; SCR_STDC: stdc_reg; diff --git a/src_Core/ISA/ISA_Decls_CHERI.bsv b/src_Core/ISA/ISA_Decls_CHERI.bsv index 684fd70..d421127 100755 --- a/src_Core/ISA/ISA_Decls_CHERI.bsv +++ b/src_Core/ISA/ISA_Decls_CHERI.bsv @@ -85,10 +85,10 @@ typedef enum { SCR_PCC = 5'd00, SCR_DDC = 5'd01, - SCR_UTCC = 5'd04, - SCR_UTDC = 5'd05, - SCR_UScratchC = 5'd06, - SCR_UEPCC = 5'd07, +// SCR_UTCC = 5'd04, +// SCR_UTDC = 5'd05, +// SCR_UScratchC = 5'd06, +// SCR_UEPCC = 5'd07, SCR_STCC = 5'd12, SCR_STDC = 5'd13,