From 449070e347ca6ef6a6e23ea94bf694afcc0d5e37 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 8 Apr 2024 10:59:33 +0100 Subject: [PATCH 1/2] Copied over preliminary Konata support from https://github.com/bluespec/Toooba/commit/89b0c37a7b28066f2852e1eb46d174bf8e2b130e The referenced commit did not merge well with our code base. Therefore, I copied over the changes manually. These changes do not constitute a working Konata support for Toooba. In this commit, I commented out some things that did not compile, which will be fixed in future --- .../RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 117 +++++++++++++++++- .../RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 40 +++++- .../RISCY_OOO/procs/lib/ReorderBuffer.bsv | 37 ++++++ 3 files changed, 190 insertions(+), 4 deletions(-) diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index a99974a..8acba4c 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -195,6 +195,9 @@ typedef struct { Maybe#(PcCompressed) pred_next_pc; Bool decode_epoch; Epoch main_epoch; +`ifdef KONATA + Bit#(64) u_id; +`endif } Fetch1ToFetch2 deriving(Bits, Eq, FShow); typedef struct { @@ -208,6 +211,9 @@ typedef struct { Bool access_mmio; // inst fetch from MMIO Bool decode_epoch; Epoch main_epoch; +`ifdef KONATA + Bit#(64) u_id; +`endif } Fetch2ToFetch3 deriving(Bits, Eq, FShow); typedef struct { @@ -220,6 +226,9 @@ typedef struct { `ifdef RVFI_DII Dii_Parcel_Id dii_pid; `endif +`ifdef KONATA + Bit#(64) u_id; +`endif } Fetch3ToDecode deriving(Bits, Eq, FShow); // Used purely internally in doDecode. @@ -238,6 +247,9 @@ typedef struct { Maybe#(Exception) cause; Bool cause_second_half; Bool mispred_first_half; +`ifdef KONATA + Bit#(64) u_id; +`endif } InstrFromFetch3 deriving(Bits, Eq, FShow); function Bool popInst(DecodeResult dr); @@ -284,6 +296,9 @@ function InstrFromFetch3 fetch3_2_instC(Fetch3ToDecode in, Instruction inst, Bit cause: in.cause, cause_second_half: False, mispred_first_half: False +`ifdef KONATA + , u_id: in.u_id +`endif }; function InstrFromFetch3 fetch3s_2_inst(Fetch3ToDecode inHi, Fetch3ToDecode inLo); @@ -314,6 +329,9 @@ typedef struct { ArchRegs regs; Maybe#(Exception) cause; Addr tval; // in case of exception +`ifdef KONATA + Bit#(64) u_id; +`endif } FromFetchStage deriving (Bits, Eq, FShow); // train next addr pred (BTB) @@ -470,6 +488,22 @@ module mkFetchStage(FetchStage); `ifdef PERFORMANCE_MONITORING Reg#(Bool) redirect_evt_reg <- mkDReg(False); `endif +`ifdef KONATA + Reg#(Bit#(64)) uid <- mkReg(0); + Reg#(Bool) k_reset <- mkReg(True); + + rule header(k_reset); + k_reset <= ! k_reset; + $display("KONATAKanata\t0004"); + $display("KONATAC=\t0"); + $fflush; + endrule + + rule displayCycle; + $display("KONATAC\t1"); + $fflush; + endrule +`endif rule updatePcInBtb; nextAddrPred.put_pc(pc_reg[pc_final_port]); @@ -520,10 +554,24 @@ module mkFetchStage(FetchStage); pred_next_pc: isValid(pred_next_pc) ? Valid(compressPc(ppc_idx, validValue(pred_next_pc))) : Invalid, decode_epoch: decode_epoch[0], - main_epoch: f_main_epoch}; + main_epoch: f_main_epoch +`ifdef KONATA + , u_id: uid +`endif + }; f12f2.enq(out); if (verbose) $display("%d Fetch1: ", cur_cycle, fshow(out), " posLastSupX2: %d", posLastSupX2); +`ifdef KONATA + Bit#(TAdd#(TLog#(SupSizeX2),1)) posLastSupX2ex = zeroExtend(posLastSupX2); + uid <= uid + fromInteger(valueof(SupSizeX2)); + for (Integer i = 0; fromInteger(i) <= posLastSupX2ex; i = i+1) + begin + $display("KONATAI\t%0d\t%0d\t0", uid + fromInteger(i), uid + fromInteger(i)); + $display("KONATAS\t%0d\t0\tF1", uid + fromInteger(i)); + $fflush; + end +`endif endrule rule doFetch2; @@ -574,7 +622,11 @@ module mkFetchStage(FetchStage); cause: cause, access_mmio: access_mmio, decode_epoch: in.decode_epoch, - main_epoch: in.main_epoch }; + main_epoch: in.main_epoch +`ifdef KONATA + , u_id: in.u_id +`endif + }; f22f3.enq(out); if (verbosity >= 2) begin @@ -582,6 +634,16 @@ module mkFetchStage(FetchStage); $display ("Fetch2: TLB response pyhs_pc 0x%0h cause ", phys_pc, fshow (cause)); $display ("Fetch2: f2_tof3.enq: out ", fshow (out)); end +`ifdef KONATA + + Bit#(TAdd#(TLog#(SupSizeX2),1)) posLastSupX2ex = zeroExtend( in.inst_frags_fetched); + for (Integer i = 0; fromInteger(i) <= posLastSupX2ex; i = i+1) + begin + $display("KONATAE\t%0d\t0\tF1", in.u_id + fromInteger(i)); + $display("KONATAS\t%0d\t0\tF2", in.u_id + fromInteger(i)); + $fflush; + end +`endif endrule // Break out of i$ @@ -630,7 +692,15 @@ module mkFetchStage(FetchStage); cause: fetch3In.cause, decode_epoch: fetch3In.decode_epoch, main_epoch: fetch3In.main_epoch +`ifdef KONATA + , u_id: fetch3In.u_id + fromInteger(i) +`endif }); +`ifdef KONATA + $display("KONATAE\t%0d\t0\tF2", fetch3In.u_id + fromInteger(i)); + $display("KONATAS\t%0d\t0\tM", fetch3In.u_id + fromInteger(i)); + $fflush; +`endif end endrule: doFetch3 @@ -643,6 +713,12 @@ module mkFetchStage(FetchStage); if (f32d.deqS[i].canDeq &&& !isCurrent(f32d.deqS[i].first)) begin pcBlocks.rPort[i].remove(f32d.deqS[i].first.pc.idx); f32d.deqS[i].deq; +`ifdef KONATA + $display("KONATAL\t%0d\t0\tWrongPathDecode %x", f32d.deqS[i].first.u_id, f32d.deqS[i].first.pc); + $display("KONATAE\t%0d\t0\tM", f32d.deqS[i].first.u_id); + $display("KONATAR\t%0d\t%0d\t1\t//KILLDECODE", f32d.deqS[i].first.u_id, f32d.deqS[i].first.u_id); + $fflush; +`endif end endrule: doDecodeFlush @@ -661,7 +737,18 @@ module mkFetchStage(FetchStage); if (frags[i] matches tagged Valid .frag) begin Fetch3ToDecode prev_frag = (i != 0) ? validValue(frags[i-1]) : ?; if (prev_frag_available &&& !is_16b_inst(prev_frag.inst_frag)) begin // 2nd half of 32-bit instruction +//`ifdef KONATA +// $display("KONATAL\t%0d\t0\tBrought Fragment %x", prev_frag.u_id, prev_frag.pc); +// $display("KONATAE\t%0d\t0\tM", prev_frag.u_id); +// $display("KONATAR\t%0d\t%0d\t1\t//MERGE FRAGMENT", prev_frag.u_id, prev_frag.u_id ); +// $fflush; +//`endif new_pick = tagged Valid fetch3s_2_inst(frag, prev_frag); +//`ifdef KONATA +// $display("KONATAE\t%0d\t0\tM", fromMaybe(?,frags[i]).u_id); +// $display("KONATAS\t%0d\t0\tD", fromMaybe(?,frags[i]).u_id); +// $fflush; +//`endif /*if (!validValue(new_pick).mispred_first_half) begin doAssert(getAddr(decompressPc(prev_frag.pc))+2 == getAddr(decompressPc(frag.pc)), "Attached fragments with non-contigious PCs"); `ifdef RVFI_DII @@ -669,6 +756,11 @@ module mkFetchStage(FetchStage); `endif end*/ end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction +//`ifdef KONATA +// $display("KONATAE\t%0d\t0\tM", fromMaybe(?,frags[i]).u_id); +// $display("KONATAS\t%0d\t0\tD", fromMaybe(?,frags[i]).u_id); +// $fflush; +//`endif new_pick = tagged Valid fetch3_2_instC(frag, fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag), zeroExtend(frag.inst_frag)); @@ -751,6 +843,12 @@ module mkFetchStage(FetchStage); // We predicted a taken branch for PC, but this is an // uncompressed instruction, so we redirect to this PC and // train it to fetch the other half in future. +`ifdef KONATA + $display("KONATAE\t%0d\t0\tD", in.u_id); + $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc); + $display("KONATAR\t%0d\t%0d\t1\t//depoch wrong", in.u_id, in.u_id); + $fflush; +`endif if (verbose) $display("mispredicted first half in decode: pc : %h", pc); decode_epoch_local = !decode_epoch_local; redirectPc = Valid (pc); // record redirect to the first PC in this bundle. @@ -842,6 +940,12 @@ module mkFetchStage(FetchStage); end // if (!isValid(cause)) if (isValid(m_push_addr)) trainInfo.ras = trainInfo.ras + 1; decode_pc_reg[i] <= getAddr(ppc); +`ifdef KONATA + $display("KONATAE\t%0d\t0\tD", in.u_id); + $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc, fshow(dInst)); + $display("KONATAS\t%0d\t0\tRnm", in.u_id); + $fflush; +`endif let out = FromFetchStage{pc: pc, `ifdef RVFI_DII dii_pid: in.dii_pid, @@ -855,6 +959,9 @@ module mkFetchStage(FetchStage); regs: decode_result.regs, cause: cause, tval: getAddr(pc) + ((in.cause_second_half) ? 2:0) +`ifdef KONATA + , u_id : in.u_id +`endif }; out_fifo.enqS[i].enq(out); if (verbosity >= 1) begin @@ -866,6 +973,12 @@ module mkFetchStage(FetchStage); end end // if (in.decode_epoch == decode_epoch_local) else begin +`ifdef KONATA + $display("KONATAE\t%0d\t0\tD", in.u_id); + $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc); + $display("KONATAR\t%0d\t%0d\t1\t//depoch wrong", in.u_id, in.u_id); + $fflush; +`endif if (verbose) $display("Drop decoded within a superscalar"); // just drop wrong path instructions end diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 7405ef5..3eb5f11 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -230,6 +230,12 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); stop = True; end else begin +`ifdef KONATA + $display("KONATAE\t%d\t0\tRnm", x.u_id); + $display("KONATAL\t%0d\t0\tWrongPathRename %x", x.u_id, x.pc); + $display("KONATAR\t%d\t%d\t1\t//KILLRENAME", x.u_id, x.u_id); + $fflush; +`endif // wrong path, kill it & update prev epoch fetchStage.pipelines[i].deq; epochManager.updatePrevEpoch[i].update(x.main_epoch); @@ -388,9 +394,17 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif `ifdef RVFI , traceBundle: unpack(0) +`endif +`ifdef KONATA + , u_id : x.u_id `endif }; rob.enqPort[0].enq(y); +`ifdef KONATA + $display("KONATAE\t%d\t0\tRnm", x.u_id); + $display("KONATAS\t%d\t0\tE", x.u_id); + $fflush; +`endif // record if we issue an interrupt if(firstTrap matches tagged Valid (tagged Interrupt .i)) begin inIfc.issueCsrInstOrInterrupt; @@ -602,10 +616,17 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif `ifdef RVFI , traceBundle: unpack(0) +`endif +`ifdef KONATA + , u_id : x.u_id `endif }; rob.enqPort[0].enq(y); - +`ifdef KONATA + $display("KONATAE\t%d\t0\tRnm", x.u_id); + $display("KONATAS\t%d\t0\tE", x.u_id); + $fflush; +`endif `ifdef PERFORMANCE_MONITORING EventsTransExe events = unpack(0); events.evt_RENAMED_INST = 1; @@ -786,10 +807,18 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); spec_bits: spec_bits `ifdef RVFI_DII , dii_pid: x.dii_pid +`endif +`ifdef KONATA + , u_id : x.u_id `endif }; rob.enqPort[0].enq(y); +`ifdef KONATA + $display("KONATAE\t%d\t0\tRnm", x.u_id); + $display("KONATAS\t%d\t0\tE", x.u_id); + $fflush; +`endif `ifdef CHECK_DEADLOCK renameCorrectPath.send; `endif @@ -1153,10 +1182,17 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif `ifdef RVFI , traceBundle: unpack(0) +`endif +`ifdef KONATA + , u_id : x.u_id `endif }; rob.enqPort[i].enq(y); - +`ifdef KONATA + $display("KONATAE\t%0d\t0\tRnm", x.u_id); + $display("KONATAS\t%0d\t0\tE", x.u_id); + $fflush; +`endif // record activity doCorrectPath = True; renameCnt = renameCnt + 1; diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index a96a64c..9f10087 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -117,6 +117,9 @@ typedef struct { `ifdef RVFI ExtraTraceBundle traceBundle; `endif +`ifdef KONATA + Bit#(64) u_id; +`endif } ToReorderBuffer deriving(Bits, FShow); typedef enum { @@ -282,6 +285,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p `ifdef RVFI Ehr#(TAdd#(2, TAdd#(fpuMulDivExeNum, aluExeNum)), ExtraTraceBundle) traceBundle <- mkEhr(?); `endif +`ifdef KONATA + Reg#(Bit#(64)) uid <- mkReg(?); +`endif // wires to get stale (EHR port 0) values of PPC Wire#(CapMem) predPcWire <- mkBypassWire; @@ -409,6 +415,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p method Action write_enq(ToReorderBuffer x); pc <= x.pc; +`ifdef KONATA + uid <= x.u_id; +`endif orig_inst <= x.orig_inst; iType <= x.iType; rg_dst_reg <= x.dst; @@ -482,6 +491,9 @@ module mkReorderBufferRowEhr(ReorderBufferRowEhr#(aluExeNum, fpuMulDivExeNum)) p traceBundle: traceBundle[traceBundle_deq_port], `endif spec_bits: spec_bits[sb_deq_port] +`ifdef KONATA + , u_id: uid +`endif }; endmethod @@ -692,6 +704,9 @@ module mkSupReorderBuffer#( Vector#(SupSize, Vector#(SingleScalarSize, Ehr#(2, Bool))) valid <- replicateM(replicateM(mkEhr(False))); Vector#(SupSize, Reg#(SingleScalarPtr)) enqP <- replicateM(mkReg(0)); Vector#(SupSize, Ehr#(2, SingleScalarPtr)) deqP_ehr <- replicateM(mkEhr(0)); +`ifdef KONATA + Vector#(SupSize, Vector#(SingleScalarSize, Ehr#(2, Bit#(64)))) uid <- replicateM(replicateM(mkEhr(0))); +`endif let deqP = getVEhrPort(deqP_ehr, 0); let deqP_wrongSpec = getVEhrPort(deqP_ehr, 1); // for overwrite deqP when killing all @@ -756,6 +771,11 @@ module mkSupReorderBuffer#( // move deqP & reset valid deqP[i] <= getNextPtr(deqP[i]); valid[i][deqP[i]][valid_deq_port] <= False; +`ifdef KONATA + let id = uid[i][deqP[i]][valid_deq_port]; + $display("KONATAR\t%0d\t%0d\t0", id, id); + $fflush; +`endif end end // update firstDeqWay: find the first deq port that is not enabled @@ -789,6 +809,13 @@ module mkSupReorderBuffer#( for(Integer w = 0; w < valueof(SupSize); w = w+1) begin for(Integer i = 0; i < valueof(SingleScalarSize); i = i+1) begin valid[w][i][valid_wrongSpec_port] <= False; +`ifdef KONATA + if (valid[w][i][valid_wrongSpec_port]) begin + $display("KONATAE\t%0d\t0\tE", uid[w][i][valid_wrongSpec_port]); + $display("KONATAR\t%0d\t%0d\t1\t//KILLALLROB", uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); + $fflush; + end +`endif end end // reset all ptrs to 0 @@ -810,6 +837,13 @@ module mkSupReorderBuffer#( for(Integer i = 0; i < valueof(SingleScalarSize); i = i+1) begin if(row[w][i].dependsOn_wrongSpec(specTag)) begin valid[w][i][valid_wrongSpec_port] <= False; +`ifdef KONATA + if (valid[w][i][valid_wrongSpec_port]) begin + $display("KONATAE\t%0d\t0\tE", uid[w][i][valid_wrongSpec_port]); + $display("KONATAR\t%0d\t%0d\t1\t//KILLMISPREDICTION", uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); + $fflush; + end +`endif end end end @@ -970,6 +1004,9 @@ module mkSupReorderBuffer#( enqP[i] <= getNextPtr(enqP[i]); row[i][enqP[i]].write_enq(x); valid[i][enqP[i]][valid_enq_port] <= True; +`ifdef KONATA + uid[i][enqP[i]][valid_enq_port] <= x.u_id; +`endif end end // update firstEnqWay: find the first enq port that is not enabled From 598ac6574e83b138cc2f917e0fd30e2e88873ac2 Mon Sep 17 00:00:00 2001 From: Franz Fuchs Date: Mon, 8 Apr 2024 13:13:27 +0100 Subject: [PATCH 2/2] Added working Konata support Konata: change M to F3 Added konata support to ALU pipeline Added KONATA support to Fpu pipeline Added KONATA support to Mem pipeline Finished v1 of KONATA support Added improvements to catch fragments in Konata Kill fragments that have been merged Fixed order of konata logs Added commit stage output Ensured that only the Commit stage can retire instructions in konata Fixed printing commit stage log for Cap instructions Changed Kanata to include the cycle counter for each line in the log file; please note that this requires post processing Added reservation station support for Konata Added parsing script for Toooba output Removed double updated to D stage Adressed Peter's comments --- builds/Resources/parse_pre_kanata.py | 60 +++++++++ .../procs/RV64G_OOO/AluExePipeline.bsv | 45 +++++++ .../RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv | 66 ++++++++- .../RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv | 127 ++++++++++++------ .../procs/RV64G_OOO/FpuMulDivExePipeline.bsv | 79 +++++++++++ .../procs/RV64G_OOO/MemExePipeline.bsv | 46 ++++++- .../RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv | 57 ++++++-- src_Core/RISCY_OOO/procs/lib/Fpu.bsv | 27 +++- src_Core/RISCY_OOO/procs/lib/MulDiv.bsv | 25 ++++ .../RISCY_OOO/procs/lib/ReorderBuffer.bsv | 21 +-- .../procs/lib/ReservationStationEhr.bsv | 28 ++++ 11 files changed, 509 insertions(+), 72 deletions(-) create mode 100755 builds/Resources/parse_pre_kanata.py diff --git a/builds/Resources/parse_pre_kanata.py b/builds/Resources/parse_pre_kanata.py new file mode 100755 index 0000000..2b24779 --- /dev/null +++ b/builds/Resources/parse_pre_kanata.py @@ -0,0 +1,60 @@ +#! /usr/bin/env python3 +# +# Copyright (c) 2024 Franz Fuchs +# All rights reserved. +# +# This software was developed by the University of Cambridge +# Department of Computer Science and Technology under the +# SIPP (Secure IoT Processor Platform with Remote Attestation) +# project funded by EPSRC: EP/S030868/1 +# +# @BERI_LICENSE_HEADER_START@ +# +# Licensed to BERI Open Systems C.I.C. (BERI) under one or more contributor +# license agreements. See the NOTICE file distributed with this work for +# additional information regarding copyright ownership. BERI licenses this +# file to you under the BERI Hardware-Software License, Version 1.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at: +# +# http://www.beri-open-systems.org/legal/license-1-0.txt +# +# Unless required by applicable law or agreed to in writing, Work distributed +# under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +# CONDITIONS OF ANY KIND, either express or implied. See the License for the +# specific language governing permissions and limitations under the License. +# +# @BERI_LICENSE_HEADER_END@ +# + +import argparse + +def parse(filename): + with open(filename, "r") as f: + cur_cycle = 0 + print("Kanata\t0004") + print("C=\t0") + for line in f: + v = line.split() + c = int(v[1]) + if(c > cur_cycle): + print("C\t{0:0d}".format((c - cur_cycle))) + cur_cycle = c + print("{0}\t{1}\t{2}\t{3}".format(v[0], v[2], v[3], v[4])) + +def main(): + parser = argparse.ArgumentParser(description=''' + Generate Kanata 0004 log file from bluespec implementation output + ''') + + parser.add_argument('logfile', type=str, help='path to logging output') + + args = parser.parse_args() + + if args.logfile: + parse(args.logfile) + else: + sys.exit("Must specify the logging output of the implementation") + +if __name__ == "__main__": + main() \ No newline at end of file diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv index 25d1bc6..80f7e30 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv @@ -6,6 +6,7 @@ // Copyright (c) 2020 Jessica Clarke // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -14,6 +15,11 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -80,6 +86,9 @@ typedef struct { PredTrainInfo trainInfo; // specualtion Maybe#(SpecTag) spec_tag; +`ifdef KONATA + Bit#(64) u_id; +`endif } AluDispatchToRegRead deriving(Bits, Eq, FShow); typedef struct { @@ -96,6 +105,9 @@ typedef struct { Bit #(32) orig_inst; // specualtion Maybe#(SpecTag) spec_tag; +`ifdef KONATA + Bit#(64) u_id; +`endif } AluRegReadToExe deriving(Bits, FShow); typedef struct { @@ -117,6 +129,9 @@ typedef struct { `ifdef RVFI ExtraTraceBundle traceBundle; `endif +`ifdef KONATA + Bit#(64) u_id; +`endif } AluExeToFinish deriving(Bits, FShow); // XXX currently ALU/Br should not have any exception, so we don't have cause feild above @@ -267,6 +282,11 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); if(x.regs.dst matches tagged Valid .dst) begin inIfc.setRegReadyAggr(dst.indx); end +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tRsvA", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tAlu1", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage dispToRegQ.enq(ToSpecFifo { @@ -276,6 +296,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); tag: x.tag, trainInfo: x.data.trainInfo, spec_tag: x.spec_tag +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: x.spec_bits }); @@ -340,6 +363,12 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); `endif `endif +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tAlu1", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tAlu2", cur_cycle, x.u_id); + $fflush; +`endif + // go to next stage regToExeQ.enq(ToSpecFifo { data: AluRegReadToExe { @@ -353,6 +382,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); ppc: ppc, orig_inst: orig_inst, spec_tag: x.spec_tag +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: dispToReg.spec_bits }); @@ -408,6 +440,11 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); Bool is_scr_or_csr = (isValid(x.dInst.scr) && x.dInst.iType == Scr) || isValid(x.dInst.csr); +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tAlu2", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tAlu3", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage exeToFinQ.enq(ToSpecFifo { data: AluExeToFinish { @@ -426,6 +463,9 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); regWriteData: getAddr(exec_result.data), memByteEn: replicate(False) }, +`endif +`ifdef KONATA + u_id: x.u_id, `endif controlFlow: exec_result.controlFlow, spec_tag: x.spec_tag @@ -466,6 +506,11 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline); `endif ); +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tAlu3\t%0d", cur_cycle, x.u_id, cur_cycle); + $display("KONATAS\t%0d\t%0d\t0\tAlu4\t%0d", cur_cycle, x.u_id, cur_cycle); + $fflush; +`endif `ifdef PERFORMANCE_MONITORING `ifdef CONTRACTS_VERIFY // get PC and PPC diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv index 85f68ce..81d4b99 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/CommitStage.bsv @@ -8,6 +8,7 @@ // Copyright (c) 2020 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -16,6 +17,10 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -74,6 +79,10 @@ import Cur_Cycle :: *; import Trace_Data2 :: *; `endif +`ifdef KONATA +import Ehr :: *; +`endif + typedef struct { // info about the inst blocking at ROB head Addr pc; @@ -401,6 +410,10 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // cycle. Vector#(SupSize, RWire#(LdStQTag)) setLSQAtCommit <- replicateM(mkRWire); +`ifdef KONATA + Vector#(SupSize, Ehr#(2, Maybe#(Bit#(64)))) printCommits <- replicateM(mkEhr(Invalid)); +`endif + for(Integer i = 0; i< valueof(SupSize); i = i+1) begin (* fire_when_enabled, no_implicit_conditions *) rule doSetLSQAtCommit(setLSQAtCommit[i].wget matches tagged Valid .tag); @@ -696,7 +709,11 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); `ifdef INCLUDE_TANDEM_VERIF f_rob_data.enq (x); // Save data to be sent to TV in rule doCommitTrap_handle, next `endif - +`ifdef KONATA + $display("KONATAL\t%0d\t%0d\t0\tTrap %x", cur_cycle, x.u_id, x.pc); + $display("KONATAR\t%0d\t%0d\t%0d\t1", cur_cycle, x.u_id, x.u_id); + $fflush; +`endif if (verbosity >= 1) begin $display ("instret:%0d PC:0x%0h instr:0x%08h", rg_serial_num, x.pc, x.orig_inst, " iType:", fshow (x.iType), " [doCommitTrap] %d", cur_cycle); @@ -1004,7 +1021,12 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); // incr inst cnt csrf.incInstret(1); - +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tAlu4", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tC", cur_cycle, x.u_id); + $fflush; + printCommits[0][1] <= tagged Valid x.u_id; +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin comSysCnt.incr(1); @@ -1283,6 +1305,27 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); end endcase if (opcode == opcMiscMem && funct3 == fnFENCE) fenceCnt = fenceCnt + 1; +`ifdef KONATA + case(x.iType) + Alu, J, Jr, Br, Auipc, Auipcc, CCall, CJAL, CJALR, Cap: begin + $display("KONATAE\t%0d\t%0d\t0\tAlu4", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tC", cur_cycle, x.u_id); + $fflush; + end + Ld, St, Lr, Sc, Amo: begin + $display("KONATAE\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tC", cur_cycle, x.u_id); + $fflush; + end + Fpu: begin + $display("KONATAE\t%0d\t%0d\t0\tFpu4", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tC", cur_cycle, x.u_id); + $fflush; + end + endcase + printCommits[i][1] <= tagged Valid x.u_id; + $fflush; +`endif end end `ifdef PERFORMANCE_MONITORING @@ -1379,6 +1422,25 @@ module mkCommitStage#(CommitInput inIfc)(CommitStage); ); endrule +`ifdef KONATA + rule doPrintCommitKONATA; + for(Integer i = 0; i < valueof(SupSize); i = i + 1) begin + if(printCommits[i][0] matches tagged Valid .u_id) begin + $display("KCommit print"); + $display("KONATAE\t%0d\t%0d\t0\tC", cur_cycle, u_id); + $display("KONATAR\t%0d\t%0d\t%0d\t0", cur_cycle, u_id, u_id); + $fflush; + end + end + endrule + + rule doMakePrintCommitInvalid; + for(Integer i = 0; i < valueof(SupSize); i = i + 1) begin + printCommits[i][0] <= Invalid; + end + endrule +`endif + // ================================================================ // INTERFACE diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv index 8acba4c..a0ccf4d 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FetchStage.bsv @@ -8,6 +8,7 @@ // Copyright (c) 2020 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -16,6 +17,10 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -373,6 +378,22 @@ typedef enum {Inst_16b, // A 16b instruction } Inst_Kind deriving (Bits, Eq, FShow); +`ifdef KONATA +typedef struct { + Bit#(64) puid; + Bit#(64) cuid; + PcCompressed pc; +} KMergedFrag deriving(Bits, Eq, FShow); +typedef struct { + Bit#(64) cuid; +} KSingleFrag deriving(Bits, Eq, FShow); +typedef union tagged { + KMergedFrag MergedFrag; + KSingleFrag SingleFrag; +} KInfo deriving (Bits, Eq, FShow); + +`endif + // ================================================================ (* synthesize *) @@ -492,17 +513,17 @@ module mkFetchStage(FetchStage); Reg#(Bit#(64)) uid <- mkReg(0); Reg#(Bool) k_reset <- mkReg(True); - rule header(k_reset); - k_reset <= ! k_reset; - $display("KONATAKanata\t0004"); - $display("KONATAC=\t0"); - $fflush; - endrule + //rule header(k_reset); + // k_reset <= ! k_reset; + // $display("KONATAKanata\t0004"); + // $display("KONATAC=\t0"); + // $fflush; + //endrule - rule displayCycle; - $display("KONATAC\t1"); - $fflush; - endrule + //rule displayCycle(!k_reset); + // $display("KONATAC\t1"); + // $fflush; + //endrule `endif rule updatePcInBtb; @@ -567,8 +588,8 @@ module mkFetchStage(FetchStage); uid <= uid + fromInteger(valueof(SupSizeX2)); for (Integer i = 0; fromInteger(i) <= posLastSupX2ex; i = i+1) begin - $display("KONATAI\t%0d\t%0d\t0", uid + fromInteger(i), uid + fromInteger(i)); - $display("KONATAS\t%0d\t0\tF1", uid + fromInteger(i)); + $display("KONATAI\t%0d\t%0d\t%0d\t0", cur_cycle, uid + fromInteger(i), uid + fromInteger(i)); + $display("KONATAS\t%0d\t%0d\t0\tF1", cur_cycle, uid + fromInteger(i)); $fflush; end `endif @@ -639,8 +660,8 @@ module mkFetchStage(FetchStage); Bit#(TAdd#(TLog#(SupSizeX2),1)) posLastSupX2ex = zeroExtend( in.inst_frags_fetched); for (Integer i = 0; fromInteger(i) <= posLastSupX2ex; i = i+1) begin - $display("KONATAE\t%0d\t0\tF1", in.u_id + fromInteger(i)); - $display("KONATAS\t%0d\t0\tF2", in.u_id + fromInteger(i)); + $display("KONATAE\t%0d\t%0d\t0\tF1", cur_cycle, in.u_id + fromInteger(i)); + $display("KONATAS\t%0d\t%0d\t0\tF2", cur_cycle, in.u_id + fromInteger(i)); $fflush; end `endif @@ -697,8 +718,8 @@ module mkFetchStage(FetchStage); `endif }); `ifdef KONATA - $display("KONATAE\t%0d\t0\tF2", fetch3In.u_id + fromInteger(i)); - $display("KONATAS\t%0d\t0\tM", fetch3In.u_id + fromInteger(i)); + $display("KONATAE\t%0d\t%0d\t0\tF2", cur_cycle, fetch3In.u_id + fromInteger(i)); + $display("KONATAS\t%0d\t%0d\t0\tF3", cur_cycle, fetch3In.u_id + fromInteger(i)); $fflush; `endif end @@ -714,9 +735,9 @@ module mkFetchStage(FetchStage); pcBlocks.rPort[i].remove(f32d.deqS[i].first.pc.idx); f32d.deqS[i].deq; `ifdef KONATA - $display("KONATAL\t%0d\t0\tWrongPathDecode %x", f32d.deqS[i].first.u_id, f32d.deqS[i].first.pc); - $display("KONATAE\t%0d\t0\tM", f32d.deqS[i].first.u_id); - $display("KONATAR\t%0d\t%0d\t1\t//KILLDECODE", f32d.deqS[i].first.u_id, f32d.deqS[i].first.u_id); + $display("KONATAL\t%0d\t%0d\t0\tWrongPathDecode %x", cur_cycle, f32d.deqS[i].first.u_id, f32d.deqS[i].first.pc); + $display("KONATAE\t%0d\t%0d\t0\tF3", cur_cycle, f32d.deqS[i].first.u_id); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//KILLDECODE", cur_cycle, f32d.deqS[i].first.u_id, f32d.deqS[i].first.u_id); $fflush; `endif end @@ -732,23 +753,19 @@ module mkFetchStage(FetchStage); Maybe#(Bit#(TLog#(SupSizeX2))) m_used_frag_count = Invalid; Bit#(TLog#(SupSize)) pick_count = 0; Bool prev_frag_available = False; +`ifdef KONATA + Vector#(SupSizeX2, Maybe#(KInfo)) kinfos = replicate(Invalid); +`endif for (Integer i = 0; i < valueOf(SupSizeX2) && !isValid(decodeIn[valueOf(SupSize) - 1]); i = i + 1) begin Maybe#(InstrFromFetch3) new_pick = Invalid; if (frags[i] matches tagged Valid .frag) begin Fetch3ToDecode prev_frag = (i != 0) ? validValue(frags[i-1]) : ?; if (prev_frag_available &&& !is_16b_inst(prev_frag.inst_frag)) begin // 2nd half of 32-bit instruction -//`ifdef KONATA -// $display("KONATAL\t%0d\t0\tBrought Fragment %x", prev_frag.u_id, prev_frag.pc); -// $display("KONATAE\t%0d\t0\tM", prev_frag.u_id); -// $display("KONATAR\t%0d\t%0d\t1\t//MERGE FRAGMENT", prev_frag.u_id, prev_frag.u_id ); -// $fflush; -//`endif +`ifdef KONATA + kinfos[i] = Valid (tagged MergedFrag ( KMergedFrag{ puid: prev_frag.u_id, cuid: fromMaybe(?,frags[i]).u_id, pc: prev_frag.pc})); +`endif new_pick = tagged Valid fetch3s_2_inst(frag, prev_frag); -//`ifdef KONATA -// $display("KONATAE\t%0d\t0\tM", fromMaybe(?,frags[i]).u_id); -// $display("KONATAS\t%0d\t0\tD", fromMaybe(?,frags[i]).u_id); -// $fflush; -//`endif + /*if (!validValue(new_pick).mispred_first_half) begin doAssert(getAddr(decompressPc(prev_frag.pc))+2 == getAddr(decompressPc(frag.pc)), "Attached fragments with non-contigious PCs"); `ifdef RVFI_DII @@ -756,11 +773,9 @@ module mkFetchStage(FetchStage); `endif end*/ end else if (is_16b_inst(frag.inst_frag) || isValid(frag.cause)) begin // 16-bit instruction -//`ifdef KONATA -// $display("KONATAE\t%0d\t0\tM", fromMaybe(?,frags[i]).u_id); -// $display("KONATAS\t%0d\t0\tD", fromMaybe(?,frags[i]).u_id); -// $fflush; -//`endif +`ifdef KONATA + kinfos[i] = Valid (tagged SingleFrag ( KSingleFrag{ cuid: fromMaybe(?,frags[i]).u_id})); +`endif new_pick = tagged Valid fetch3_2_instC(frag, fv_decode_C (misa, misa_mxl_64, getFlags(decompressPc(frag.pc))==1, frag.inst_frag), zeroExtend(frag.inst_frag)); @@ -797,6 +812,30 @@ module mkFetchStage(FetchStage); delay_epoch = delay_epoch || delayForPop; `endif +`ifdef KONATA + rule doPrintFragKONATA; + for (Integer i = 0; i < valueOf(SupSizeX2); i = i + 1) begin + if(kinfos[i] matches tagged Valid .k) begin + $display(k); + $fflush; + if(k matches tagged MergedFrag .m) begin + $display("KONATAL\t%0d\t%0d\t0\tBrought Fragment %x", cur_cycle, m.puid, m.pc); + $display("KONATAE\t%0d\t%0d\t0\tF3", cur_cycle, m.puid); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//MERGE FRAGMENT", cur_cycle, m.puid, m.puid); + $display("KONATAE\t%0d\t%0d\t0\tF3", cur_cycle, m.cuid); + $display("KONATAS\t%0d\t%0d\t0\tD", cur_cycle, m.cuid); + $fflush; + end + else if(k matches tagged SingleFrag .s) begin + $display("KONATAE\t%0d\t%0d\t0\tF3", cur_cycle, s.cuid); + $display("KONATAS\t%0d\t%0d\t0\tD", cur_cycle, s.cuid); + $fflush; + end + end + end + endrule +`endif + rule doDecode(f32d.deqS[0].canDeq && isCurrent(f32d.deqS[0].first) && !delay_epoch); if (m_used_frag_count matches tagged Valid .used_frag_count) begin for (Integer i = 0; i < valueOf(SupSizeX2) && fromInteger(i) <= used_frag_count; i = i + 1) f32d.deqS[i].deq; @@ -844,9 +883,9 @@ module mkFetchStage(FetchStage); // uncompressed instruction, so we redirect to this PC and // train it to fetch the other half in future. `ifdef KONATA - $display("KONATAE\t%0d\t0\tD", in.u_id); - $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc); - $display("KONATAR\t%0d\t%0d\t1\t//depoch wrong", in.u_id, in.u_id); + $display("KONATAE\t%0d\t%0d\t0\tD", cur_cycle, in.u_id); + $display("KONATAL\t%0d\t%0d\t0\t%x ", cur_cycle, in.u_id, pc); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//depoch wrong", cur_cycle, in.u_id, in.u_id); $fflush; `endif if (verbose) $display("mispredicted first half in decode: pc : %h", pc); @@ -941,9 +980,9 @@ module mkFetchStage(FetchStage); if (isValid(m_push_addr)) trainInfo.ras = trainInfo.ras + 1; decode_pc_reg[i] <= getAddr(ppc); `ifdef KONATA - $display("KONATAE\t%0d\t0\tD", in.u_id); - $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc, fshow(dInst)); - $display("KONATAS\t%0d\t0\tRnm", in.u_id); + //$display("KONATAE\t%0d\t%0d\t0\tF3", cur_cycle, in.u_id); + $display("KONATAL\t%0d\t%0d\t0\t%x ", cur_cycle, in.u_id, getAddr(pc), fshow(dInst.iType)); + //$display("KONATAS\t%0d\t%0d\t0\tD", cur_cycle, in.u_id); $fflush; `endif let out = FromFetchStage{pc: pc, @@ -974,9 +1013,9 @@ module mkFetchStage(FetchStage); end // if (in.decode_epoch == decode_epoch_local) else begin `ifdef KONATA - $display("KONATAE\t%0d\t0\tD", in.u_id); - $display("KONATAL\t%0d\t0\t%x ", in.u_id, pc); - $display("KONATAR\t%0d\t%0d\t1\t//depoch wrong", in.u_id, in.u_id); + $display("KONATAE\t%0d\t%0d\t0\tD", cur_cycle, in.u_id); + $display("KONATAL\t%0d\t%0d\t0\t%x ", cur_cycle, in.u_id, pc); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//depoch wrong", cur_cycle, in.u_id, in.u_id); $fflush; `endif if (verbose) $display("Drop decoded within a superscalar"); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv index 3059123..7bc168d 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/FpuMulDivExePipeline.bsv @@ -4,6 +4,7 @@ //- // RVFI_DII + CHERI modifications: // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -12,6 +13,11 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -56,12 +62,19 @@ import CHERICap::*; import CHERICC_Fat::*; import ISA_Decls_CHERI::*; +`ifdef KONATA +import Cur_Cycle :: *; +`endif + typedef struct { // inst info ExecFunc execFunc; PhyRegs regs; InstTag tag; // FpuMulDiv must not have valid spec tag +`ifdef KONATA + Bit#(64) u_id; +`endif } FpuMulDivDispatchToRegRead deriving(Bits, Eq, FShow); typedef struct { @@ -73,6 +86,9 @@ typedef struct { Data rVal1; Data rVal2; Data rVal3; +`ifdef KONATA + Bit#(64) u_id; +`endif } FpuMulDivRegReadToExe deriving(Bits, Eq, FShow); typedef struct { @@ -172,12 +188,20 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); // FPU MUL DIV never have exception or misprecition, so no spec tag doAssert(!isValid(x.spec_tag), "FpuMulDiv should not carry any spec tag"); +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tRsvF", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tFpu1", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage dispToRegQ.enq(ToSpecFifo { data: FpuMulDivDispatchToRegRead { execFunc: x.data.execFunc, regs: x.regs, tag: x.tag +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: x.spec_bits }); @@ -210,6 +234,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rVal3 <- readRFBypass(src3, regsReady.src3, inIfc.rf_rd3(src3), bypassWire); end +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tFpu1", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tFpu2", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage regToExeQ.enq(ToSpecFifo { data: FpuMulDivRegReadToExe { @@ -219,6 +248,9 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rVal1: rVal1, rVal2: rVal2, rVal3: rVal3 +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: dispToReg.spec_bits }); @@ -237,10 +269,24 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); Data rVal3 = x.rVal3; case (x.execFunc) matches tagged Fpu .fpu_inst: begin +`ifdef KONATA + fpuExec.exec(fpu_inst, rVal1, rVal2, rVal3, x.dst, x.tag, spec_bits, x.u_id); + $display("KONATAE\t%0d\t%0d\t0\tFpu2", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tFpu3", cur_cycle, x.u_id); + $fflush; +`else fpuExec.exec(fpu_inst, rVal1, rVal2, rVal3, x.dst, x.tag, spec_bits); +`endif end tagged MulDiv .muldiv_inst: begin +`ifdef KONATA + mulDivExec.exec(muldiv_inst, rVal1, rVal2, x.dst, x.tag, spec_bits, x.u_id); + $display("KONATAE\t%0d\t%0d\t0\tFpu2", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tFpu3", cur_cycle, x.u_id); + $fflush; +`else mulDivExec.exec(muldiv_inst, rVal1, rVal2, x.dst, x.tag, spec_bits); +`endif end default: begin doAssert(False, "unknown execFunc for doExeFpuMulDiv"); @@ -248,13 +294,22 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); endcase endrule +`ifdef KONATA + function Action doFinish(Maybe#(PhyDst) dst, InstTag tag, Data data, Bit#(5) fflags, Bit#(64) u_id); +`else function Action doFinish(Maybe#(PhyDst) dst, InstTag tag, Data data, Bit#(5) fflags); +`endif action // write to register file if(dst matches tagged Valid .valid_dst) begin inIfc.writeRegFile(valid_dst.indx, data); end // update the instruction in the reorder buffer. +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tFpu3", cur_cycle, u_id); + $display("KONATAS\t%0d\t%0d\t0\tFpu4", cur_cycle, u_id); + $fflush; +`endif inIfc.rob_setExecuted(tag, `ifdef INCLUDE_TANDEM_VERIF data, @@ -275,13 +330,21 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rule doFinishFpSimple; FpuResp resp <- fpuExec.simpleResp; if(verbose) $display("[doFinishFpSimple] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags); +`endif endrule rule doFinishFpFma; FpuResp resp <- fpuExec.fmaResp; if(verbose) $display("[doFinishFpFma] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags); +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin exeFpFmaCnt.incr(1); @@ -292,7 +355,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rule doFinishFpDiv; FpuResp resp <- fpuExec.divResp; if(verbose) $display("[doFinishFpDiv] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags); +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin exeFpDivCnt.incr(1); @@ -303,7 +370,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rule doFinishFpSqrt; FpuResp resp <- fpuExec.sqrtResp; if(verbose) $display("[doFinishFpSqrt] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.res.data, resp.res.fflags); +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin exeFpSqrtCnt.incr(1); @@ -314,7 +385,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rule doFinishIntMul; MulDivResp resp <- mulDivExec.mulResp; if(verbose) $display("[doFinishIntMul] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.data, 0, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.data, 0); +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin exeIntMulCnt.incr(1); @@ -325,7 +400,11 @@ module mkFpuMulDivExePipeline#(FpuMulDivExeInput inIfc)(FpuMulDivExePipeline); rule doFinishIntDiv; MulDivResp resp <- mulDivExec.divResp; if(verbose) $display("[doFinishIntDiv] ", fshow(resp)); +`ifdef KONATA + doFinish(resp.dst, resp.tag, resp.data, 0, resp.u_id); +`else doFinish(resp.dst, resp.tag, resp.data, 0); +`endif `ifdef PERF_COUNT if(inIfc.doStats) begin exeIntDivCnt.incr(1); diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv index 46ed78a..3f572f3 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv @@ -6,6 +6,7 @@ // Copyright (c) 2020 Alexandre Joannou // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -14,6 +15,11 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -87,6 +93,9 @@ typedef struct { LdStQTag ldstq_tag; CapChecks cap_checks; Bool ddc_offset; +`ifdef KONATA + Bit#(64) u_id; +`endif } MemDispatchToRegRead deriving(Bits, Eq, FShow); typedef struct { @@ -99,6 +108,9 @@ typedef struct { CapPipe rVal1; CapPipe rVal2; CapChecks cap_checks; +`ifdef KONATA + Bit#(64) u_id; +`endif } MemRegReadToExe deriving(Bits, FShow); typedef struct { @@ -119,6 +131,9 @@ typedef struct { Bool allowCapLoad; Maybe#(CSR_XCapCause) capException; Maybe#(BoundsCheck) check; +`ifdef KONATA + Bit#(64) u_id; +`endif } MemExeToFinish deriving(Bits, FShow); // bookkeeping when waiting for MMIO resp which may cause exception @@ -461,7 +476,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); // executed after address transation doAssert(!(x.data.mem_func == St && isValid(x.regs.dst)), "St cannot have dst reg"); - +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tRsvM", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tMem1", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage dispToRegQ.enq(ToSpecFifo { data: MemDispatchToRegRead { @@ -472,6 +491,9 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); ldstq_tag: x.data.ldstq_tag, cap_checks: x.data.cap_checks, ddc_offset: x.data.ddc_offset +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: x.spec_bits }); @@ -507,7 +529,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); if(x.regs.src2 matches tagged Valid .src2 &&& src2 != 0) begin rVal2 <- readRFBypass(src2, regsReady.src2, inIfc.rf_rd2(src2), bypassWire); end - +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tMem1", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tMem2", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage regToExeQ.enq(ToSpecFifo { data: MemRegReadToExe { @@ -518,6 +544,9 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); rVal1: rVal1, rVal2: rVal2, cap_checks: x.cap_checks +`ifdef KONATA + , u_id: x.u_id +`endif }, spec_bits: dispToReg.spec_bits }); @@ -577,6 +606,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); accessByteCount = fromInteger(valueOf(CacheUtils::CLineNumMemDataBytes)); end +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tMem2", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tMem3", cur_cycle, x.u_id); + $fflush; +`endif // go to next stage by sending to TLB dTlb.procReq(DTlbReq { inst: MemExeToFinish { @@ -595,6 +629,9 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); capException: capChecksMem(x.rVal1, x.rVal2, x.cap_checks, x.mem_func, origBE), check: prepareBoundsCheck(x.rVal1, x.rVal2, almightyCap/*ToDo: pcc*/, ddc, getAddr(vaddr), accessByteCount, x.cap_checks) +`ifdef KONATA + , u_id: x.u_id +`endif }, specBits: regToExe.spec_bits }); @@ -703,6 +740,11 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline); `endif `endif +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tMem3", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tMem4", cur_cycle, x.u_id); + $fflush; +`endif // update LSQ LSQUpdateAddrResult updRes <- lsq.updateAddr( x.ldstq_tag, cause, x.allowCapLoad && allowCapPTE, paddr, isMMIO, x.shiftedBE diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv index 3eb5f11..d935830 100644 --- a/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv +++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv @@ -7,6 +7,7 @@ // Copyright (c) 2020 Jessica Clarke // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -15,6 +16,11 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -231,9 +237,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); end else begin `ifdef KONATA - $display("KONATAE\t%d\t0\tRnm", x.u_id); - $display("KONATAL\t%0d\t0\tWrongPathRename %x", x.u_id, x.pc); - $display("KONATAR\t%d\t%d\t1\t//KILLRENAME", x.u_id, x.u_id); + $display("KONATAE\t%0d\t%d\t0\tRnm", cur_cycle, x.u_id); + $display("KONATAL\t%0d\t%0d\t0\tWrongPathRename %x", cur_cycle, x.u_id, x.pc); + $display("KONATAR\t%0d\t%d\t%d\t1\t//KILLRENAME", cur_cycle, x.u_id, x.u_id); $fflush; `endif // wrong path, kill it & update prev epoch @@ -401,8 +407,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); }; rob.enqPort[0].enq(y); `ifdef KONATA - $display("KONATAE\t%d\t0\tRnm", x.u_id); - $display("KONATAS\t%d\t0\tE", x.u_id); + $display("KONATAE\t%0d\t%d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%d\t0\tC", cur_cycle, x.u_id); $fflush; `endif // record if we issue an interrupt @@ -563,6 +569,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); spec_bits: spec_bits, spec_tag: Invalid, regs_ready: regs_ready_aggr // alu will recv bypass +`ifdef KONATA + , u_id: x.u_id +`endif }); end @@ -623,8 +632,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); }; rob.enqPort[0].enq(y); `ifdef KONATA - $display("KONATAE\t%d\t0\tRnm", x.u_id); - $display("KONATAS\t%d\t0\tE", x.u_id); + $display("KONATAE\t%0d\t%d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%d\t0\tRnm", cur_cycle, x.u_id); $fflush; `endif `ifdef PERFORMANCE_MONITORING @@ -815,8 +824,8 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); rob.enqPort[0].enq(y); `ifdef KONATA - $display("KONATAE\t%d\t0\tRnm", x.u_id); - $display("KONATAS\t%d\t0\tE", x.u_id); + $display("KONATAE\t%0d\t%d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%d\t0\tRnm", cur_cycle, x.u_id); $fflush; `endif `ifdef CHECK_DEADLOCK @@ -1032,6 +1041,11 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); if(scheduleRS(aluRSCount, aluReady) matches tagged Valid .k) begin // can process, send to ALU rs aluExeUsed[k] = True; // mark resource used +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tRnm", cur_cycle, x.u_id); + $fflush; +`endif reservationStationAlu[k].enq(ToReservationStation { data: AluRSData {dInst: dInst, trainInfo: trainInfo}, regs: phy_regs, @@ -1039,6 +1053,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); spec_bits: spec_bits, spec_tag: spec_tag, regs_ready: regs_ready_aggr // alu will recv bypass +`ifdef KONATA + , u_id: x.u_id +`endif }); end else begin @@ -1052,6 +1069,11 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); if(scheduleRS(fpuMulDivRSCount, fpuMulDivReady) matches tagged Valid .k) begin // can process, send to FPU MUL DIV rs fpuMulDivExeUsed[k] = True; // mark resource used +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tRnm", cur_cycle, x.u_id); + $fflush; +`endif reservationStationFpuMulDiv[k].enq(ToReservationStation { data: FpuMulDivRSData {execFunc: dInst.execFunc}, regs: phy_regs, @@ -1059,6 +1081,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); spec_bits: spec_bits, spec_tag: spec_tag, regs_ready: regs_ready_aggr // fpu mul div recv bypass +`ifdef KONATA + , u_id: x.u_id +`endif }); doAssert(ppc == fallthrough_pc, "FpuMulDiv next PC is not PC+4/PC+2"); doAssert(!isValid(dInst.csr), "FpuMulDiv never explicitly read/write CSR"); @@ -1078,6 +1103,11 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); // can process, send to Mem rs and LSQ memExeUsed = True; // mark resource used lsq_tag = lsqTag; // record LSQ tag +`ifdef KONATA + $display("KONATAE\t%0d\t%0d\t0\tD", cur_cycle, x.u_id); + $display("KONATAS\t%0d\t%0d\t0\tRnm", cur_cycle, x.u_id); + $fflush; +`endif if (dInst.iType != Fence) begin // fence does not go to RS reservationStationMem.enq(ToReservationStation { data: MemRSData { @@ -1092,6 +1122,9 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); spec_bits: spec_bits, spec_tag: spec_tag, regs_ready: regs_ready_aggr // mem currently recv bypass +`ifdef KONATA + , u_id: x.u_id +`endif }); end doAssert(ppc == fallthrough_pc, "Mem next PC is not PC+4/PC+2"); @@ -1188,11 +1221,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage); `endif }; rob.enqPort[i].enq(y); -`ifdef KONATA - $display("KONATAE\t%0d\t0\tRnm", x.u_id); - $display("KONATAS\t%0d\t0\tE", x.u_id); - $fflush; -`endif + // record activity doCorrectPath = True; renameCnt = renameCnt + 1; diff --git a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv index 37e72f0..405f6b5 100644 --- a/src_Core/RISCY_OOO/procs/lib/Fpu.bsv +++ b/src_Core/RISCY_OOO/procs/lib/Fpu.bsv @@ -75,12 +75,20 @@ typedef struct { Maybe#(PhyDst) dst; InstTag tag; // spec bits is not used in later stage, so not included here +`ifdef KONATA + Bit#(64) u_id; +`endif } FpuResp deriving(Bits, Eq, FShow); interface FpuExec; // input req +`ifdef KONATA method Action exec(FpuInst fpu_inst, Data rVal1, Data rVal2, Data rVal3, - Maybe#(PhyDst) dst, InstTag tag, SpecBits specBits); + Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits, Bit#(64) u_id); +`else + method Action exec(FpuInst fpu_inst, Data rVal1, Data rVal2, Data rVal3, + Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits); +`endif // output method ActionValue#(FpuResp) simpleResp; method ActionValue#(FpuResp) fmaResp; @@ -737,6 +745,9 @@ typedef struct { // generic bookkeeping Maybe#(PhyDst) dst; InstTag tag; +`ifdef KONATA + Bit#(64) u_id; +`endif } FpuExecInfo deriving(Bits, Eq, FShow); typedef SpecPoisonFifo#(n, FpuExecInfo) FpuExecQ#(numeric type n); @@ -815,6 +826,9 @@ module mkFpuExecPipeline(FpuExec); res: res, dst: info.dst, tag: info.tag +`ifdef KONATA + , u_id: info.u_id +`endif }; endfunction @@ -832,8 +846,13 @@ module mkFpuExecPipeline(FpuExec); let x <- double_sqrt.response.get; endrule +`ifdef KONATA + method Action exec(FpuInst fpu_inst, Data rVal1, Data rVal2, Data rVal3, + Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits, Bit#(64) u_id); +`else method Action exec(FpuInst fpu_inst, Data rVal1, Data rVal2, Data rVal3, Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits); +`endif // Convert the Risc-V RVRoundMode to FloatingPoint::RoundMode FpuRoundMode fpu_rm = (case (fpu_inst.rm) rmRNE: Rnd_Nearest_Even; @@ -899,6 +918,9 @@ module mkFpuExecPipeline(FpuExec); negateResult: fpu_inst.func == FNMSub || fpu_inst.func == FNMAdd, dst: dst, tag: tag +`ifdef KONATA + , u_id : u_id +`endif }; case (fpu_inst.func) FAdd, FSub, FMul, FMAdd, FMSub, FNMSub, FNMAdd: begin @@ -927,6 +949,9 @@ module mkFpuExecPipeline(FpuExec); res: fpu_result, dst: dst, tag: tag +`ifdef KONATA + , u_id: u_id +`endif }, spec_bits: spec_bits }); diff --git a/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv b/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv index dd8ffe3..d048eaa 100644 --- a/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv +++ b/src_Core/RISCY_OOO/procs/lib/MulDiv.bsv @@ -82,12 +82,20 @@ typedef struct { Maybe#(PhyDst) dst; InstTag tag; // spec bits is not used in later stage, so not included here +`ifdef KONATA + Bit#(64) u_id; +`endif } MulDivResp deriving(Bits, Eq, FShow); interface MulDivExec; // input req +`ifdef KONATA + method Action exec(MulDivInst mdInst, Data rVal1, Data rVal2, + Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits, Bit#(64) u_id); +`else method Action exec(MulDivInst mdInst, Data rVal1, Data rVal2, Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits); +`endif // output method ActionValue#(MulDivResp) mulResp; method ActionValue#(MulDivResp) divResp; @@ -102,6 +110,9 @@ typedef struct { // generic bookkeepings Maybe#(PhyDst) dst; InstTag tag; +`ifdef KONATA + Bit#(64) u_id; +`endif } MulDivExecInfo deriving(Bits, Eq, FShow); typedef SpecPoisonFifo#(`BOOKKEEPING_INT_MUL_SIZE, MulDivExecInfo) MulExecQ; @@ -138,8 +149,13 @@ module mkMulDivExec(MulDivExec); divUnit.deqResp; endrule +`ifdef KONATA + method Action exec(MulDivInst mdInst, Data rVal1, Data rVal2, + Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits, Bit#(64) u_id); +`else method Action exec(MulDivInst mdInst, Data rVal1, Data rVal2, Maybe#(PhyDst) dst, InstTag tag, SpecBits spec_bits); +`endif if(verbose) begin $display("[MulDiv] ", fshow(mdInst), ", ", fshow(rVal1), ", ", fshow(rVal2)); @@ -162,6 +178,9 @@ module mkMulDivExec(MulDivExec); w: mdInst.w, dst: dst, tag: tag +`ifdef KONATA + , u_id: u_id +`endif }; if(isMulFunc(mdInst.func)) begin mulUnit.req(a, b, getXilinxMulSign(mdInst.sign), ?); @@ -199,6 +218,9 @@ module mkMulDivExec(MulDivExec); data: data, dst: info.dst, tag: info.tag +`ifdef KONATA + , u_id: info.u_id +`endif }; endmethod @@ -221,6 +243,9 @@ module mkMulDivExec(MulDivExec); data: data, dst: info.dst, tag: info.tag +`ifdef KONATA + , u_id: info.u_id +`endif }; endmethod diff --git a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv index 9f10087..67536ae 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReorderBuffer.bsv @@ -5,6 +5,7 @@ // RVFI_DII + CHERI modifications: // Copyright (c) 2020 Peter Rugg // Copyright (c) 2020 Jonathan Woodruff +// Copyright (c) 2024 Franz Fuchs // All rights reserved. // // This software was developed by SRI International and the University of @@ -13,6 +14,10 @@ // DARPA SSITH research programme. // // This work was supported by NCSC programme grant 4212611/RFA 15971 ("SafeBet"). +// This software was developed by the University of Cambridge +// Department of Computer Science and Technology under the +// SIPP (Secure IoT Processor Platform with Remote Attestation) +// project funded by EPSRC: EP/S030868/1 //- // // Permission is hereby granted, free of charge, to any person @@ -771,11 +776,11 @@ module mkSupReorderBuffer#( // move deqP & reset valid deqP[i] <= getNextPtr(deqP[i]); valid[i][deqP[i]][valid_deq_port] <= False; -`ifdef KONATA - let id = uid[i][deqP[i]][valid_deq_port]; - $display("KONATAR\t%0d\t%0d\t0", id, id); - $fflush; -`endif +//`ifdef KONATA +// let id = uid[i][deqP[i]][valid_deq_port]; +// $display("KONATAR\t%0d\t%0d\t0", id, id); +// $fflush; +//`endif end end // update firstDeqWay: find the first deq port that is not enabled @@ -811,8 +816,7 @@ module mkSupReorderBuffer#( valid[w][i][valid_wrongSpec_port] <= False; `ifdef KONATA if (valid[w][i][valid_wrongSpec_port]) begin - $display("KONATAE\t%0d\t0\tE", uid[w][i][valid_wrongSpec_port]); - $display("KONATAR\t%0d\t%0d\t1\t//KILLALLROB", uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//KILLALLROB", cur_cycle, uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); $fflush; end `endif @@ -839,8 +843,7 @@ module mkSupReorderBuffer#( valid[w][i][valid_wrongSpec_port] <= False; `ifdef KONATA if (valid[w][i][valid_wrongSpec_port]) begin - $display("KONATAE\t%0d\t0\tE", uid[w][i][valid_wrongSpec_port]); - $display("KONATAR\t%0d\t%0d\t1\t//KILLMISPREDICTION", uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); + $display("KONATAR\t%0d\t%0d\t%0d\t1\t//KILLMISPREDICTION", cur_cycle, uid[w][i][valid_wrongSpec_port], uid[w][i][valid_wrongSpec_port]); $fflush; end `endif diff --git a/src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv b/src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv index b0a834b..6c8eec8 100644 --- a/src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv +++ b/src_Core/RISCY_OOO/procs/lib/ReservationStationEhr.bsv @@ -31,6 +31,10 @@ import Ehr::*; import GetPut::*; import Assert::*; +`ifdef KONATA +import Cur_Cycle :: *; +`endif + typedef struct{ a data; PhyRegs regs; @@ -40,6 +44,9 @@ typedef struct{ Maybe#(SpecTag) spec_tag; // scheduling RegsReady regs_ready; +`ifdef KONATA + Bit#(64) u_id; +`endif } ToReservationStation#(type a) deriving(Bits, Eq, FShow); interface ReservationStation#( @@ -99,6 +106,9 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)( Vector#(size, Reg#(Maybe#(SpecTag))) spec_tag <- replicateM(mkRegU); Vector#(size, Ehr#(2, SpecBits)) spec_bits <- replicateM(mkEhr(?)); Vector#(size, Ehr#(regsReadyPortNum, RegsReady)) regs_ready <- replicateM(mkEhr(?)); +`ifdef KONATA + Vector#(size, Reg#(Bit#(64))) uid <- replicateM(mkRegU); +`endif // wrong spec conflict with enq and dispatch RWire#(void) wrongSpec_enq_conflict <- mkRWire; @@ -161,6 +171,18 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)( return r; endfunction Vector#(size, Bool) can_schedule = zipWith( \&& , readVEhr(valid_dispatch_port, valid), map(get_ready, ready_wire) ); + +`ifdef KONATA + rule printRsvKonata; + for(Integer i = 0; i < valueof(size); i = i + 1) begin + if(!can_schedule[i] && valid[i][valid_dispatch_port]) begin + $display("KONATAE\t%0d\t%0d\t0\tRnm", cur_cycle, uid[i]); + $display("KONATAS\t%0d\t%0d\t0\tRsv", cur_cycle, uid[i]); + $fflush; + end + end + endrule +`endif // oldest index to dispatch let can_schedule_index = findOldest(can_schedule); @@ -225,6 +247,9 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)( spec_tag[idx] <= x.spec_tag; spec_bits[idx][sb_enq_port] <= x.spec_bits; regs_ready[idx][ready_enq_port] <= x.regs_ready; +`ifdef KONATA + uid[idx] <= x.u_id; +`endif // conflict with wrong spec wrongSpec_enq_conflict.wset(?); endmethod @@ -247,6 +272,9 @@ module mkReservationStation#(Bool lazySched, Bool lazyEnq, Bool countValid)( src3: True, dst: True } +`ifdef KONATA + , u_id: uid[i] +`endif }; endmethod