From 35524a2a5024c93499b044a922851371fc786d84 Mon Sep 17 00:00:00 2001
From: Karlis Susters <ks980@cam.ac.uk>
Date: Thu, 18 May 2023 13:34:39 +0100
Subject: [PATCH] Revert L1 store counters to tracking stores

---
 src_Core/RISCY_OOO/coherence/src/L1Bank.bsv | 38 +++------------------
 1 file changed, 4 insertions(+), 34 deletions(-)

diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
index 2bb5045..9989a09 100644
--- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
@@ -156,7 +156,7 @@ module mkL1Bank#(
     Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
 );
 
-   Bool verbose = True;
+   Bool verbose = False;
 
     L1CRqMshr#(cRqNum, wayT, tagT, procRqT) cRqMshr <- mkL1CRqMshrLocal;
 
@@ -191,15 +191,6 @@ module mkL1Bank#(
     let prefetcher <- mkL1DPrefetcher;
     let llcPrefetcher <- mkLLDPrefetcherInL1D;
 
-    Count#(Bit#(8)) addedCRqs <- mkCount(0);
-    Count#(Bit#(8)) removedCRqs <- mkCount(0);
-
-    Count#(Bit#(64)) currentFullCacheCycles <- mkCount(0);
-    Reg#(Bit#(64)) lastReportedFullCacheCycles <- mkReg(0);
-
-    Count#(Bit#(64)) sentPrefetchReq <- mkCount(0);
-    Reg#(Bit#(64)) lastReportedSentPrefetchReq <- mkReg(0);
-
     // security flush
 `ifdef SECURITY_CACHES
     Reg#(Bool) flushDone <- mkReg(True);
@@ -242,12 +233,9 @@ action
 `endif
 `ifdef PERFORMANCE_MONITORING
     EventsL1D events = unpack (0);
-    events.evt_ST = saturating_truncate(currentFullCacheCycles - lastReportedFullCacheCycles);
-    lastReportedFullCacheCycles <= currentFullCacheCycles;
-    $display("Reporting full cache cycles: %d", events.evt_ST);
     case(op)
         Ld: events.evt_LD = 1;
-        //St: events.evt_ST = 1;
+        St: events.evt_ST = 1;
         Lr, Sc, Amo: events.evt_AMO = 1;
     endcase
     perf_events[0] <= events;
@@ -279,9 +267,6 @@ action
 `endif
 `ifdef PERFORMANCE_MONITORING
     EventsL1D events = unpack (0);
-    events.evt_ST_MISS = saturating_truncate(sentPrefetchReq - lastReportedSentPrefetchReq);
-    lastReportedSentPrefetchReq <= sentPrefetchReq;
-    $display("Reporting sent prefetch req: %d", events.evt_ST_MISS);
     case(op)
         Ld: begin
             events.evt_LD_MISS_LAT = saturating_truncate(lat);
@@ -289,7 +274,7 @@ action
         end
         St: begin
             events.evt_ST_MISS_LAT = saturating_truncate(lat);
-            //events.evt_ST_MISS = 1;
+            events.evt_ST_MISS = 1;
         end
         Lr, Sc, Amo: begin
             events.evt_AMO_MISS_LAT = saturating_truncate(lat);
@@ -320,7 +305,6 @@ endfunction
             mshrIdx: n
         }));
         cRqIsPrefetch[n] <= False;
-        addedCRqs.incr(1);
        if (verbose)
         $display("%t L1 %m cRqTransfer_retry: ", $time,
             fshow(n), " ; ",
@@ -334,7 +318,6 @@ endfunction
     rule cRqTransfer_new(!cRqRetryIndexQ.notEmpty && flushDone);
         procRqT r <- toGet(rqFromCQ).get;
         cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r);
-        addedCRqs.incr(1);
         // send to pipeline
         pipeline.send(CRq (L1PipeRqIn {
             addr: r.addr,
@@ -380,19 +363,10 @@ endfunction
     endrule
 
 
-    rule print_cRqIndexQ_len;
-        //$display("L1D cRqIndexQ length= %d", addedCRqs-removedCRqs);
-    endrule
-
-    rule incrFullCacheCycles (addedCRqs - removedCRqs == 8);
-        currentFullCacheCycles.incr(1);
-    endrule
-
     (* descending_urgency = "pRsTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
     (* descending_urgency = "pRqTransfer, cRqTransfer_retry, cRqTransfer_new, createPrefetchRq" *)
-    rule createPrefetchRq(flushDone && addedCRqs - removedCRqs < 6);
+    rule createPrefetchRq(flushDone);
         Addr addr <- prefetcher.getNextPrefetchAddr;
-        sentPrefetchReq.incr(1);
         procRqT r = ProcRq {
             id: ?, //Or maybe do 0 here
             addr: addr,
@@ -405,7 +379,6 @@ endfunction
             pcHash: ?
         };
         cRqIdxT n <- cRqMshr.cRqTransfer.getEmptyEntryInit(r);
-        addedCRqs.incr(1);
         // send to pipeline
         pipeline.send(CRq (L1PipeRqIn {
             addr: r.addr,
@@ -676,7 +649,6 @@ endfunction
             );
             // release MSHR entry
             cRqMshr.pipelineResp.releaseEntry(n);
-            removedCRqs.incr(1);
         end
         else begin
             processAmo <= Valid (AmoHitInfo {
@@ -739,7 +711,6 @@ endfunction
         );
         // release MSHR entry
         cRqMshr.pipelineResp.releaseEntry(n);
-        removedCRqs.incr(1);
         // reset state
         processAmo <= Invalid;
     endrule
@@ -781,7 +752,6 @@ endfunction
             end
             // release MSHR entry
             cRqMshr.pipelineResp.releaseEntry(n);
-            removedCRqs.incr(1);
            if (verbose)
             $display("%t L1 %m pipelineResp: Sc early fail func: ", $time,
                 fshow(resetOwner), " ; ",