From 364b1d1cf3d563d3cb83f55d9c00c19ef644213f Mon Sep 17 00:00:00 2001
From: Niraj Nayan Sharma <184077001@iitb.ac.in>
Date: Fri, 3 Jan 2020 16:59:34 +0530
Subject: [PATCH] For src_SSITH_P3 builds, added conditions to include/exclude
 simulation models of the integer divider

---
 src_SSITH_P3/Makefile   |  6 +++++-
 src_SSITH_P3/README.txt | 10 ++++++++--
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/src_SSITH_P3/Makefile b/src_SSITH_P3/Makefile
index f6ec322..9cc95fb 100644
--- a/src_SSITH_P3/Makefile
+++ b/src_SSITH_P3/Makefile
@@ -38,7 +38,11 @@ BSC_COMPILATION_FLAGS += \
 
 #================================================================
 # Parameter settings for MIT RISCY
-# We omit 'BSC_COMPILATION_FLAGS += D BSIM' so it'll use Xilinx IP for floating point arith
+# We include 'BSC_COMPILATION_FLAGS += D BSIM' to use simulation
+# models for the integer divier. Omit this for synthesis.
+ifeq ($(SIM), true)
+        BSC_COMPILATION_FLAGS += -D BSIM
+endif
 
 include $(REPO)/builds/Resources/Include_RISCY_Config.mk
 
diff --git a/src_SSITH_P3/README.txt b/src_SSITH_P3/README.txt
index 2fb1595..f90a2b7 100644
--- a/src_SSITH_P3/README.txt
+++ b/src_SSITH_P3/README.txt
@@ -29,9 +29,15 @@ into this socket:
     - Variations/alternatives by various SSITH project teams
 
 >================================================================
-Whenever there are changes to the Piccolo core, rerun:
+Whenever there are changes to the Toooba core, rerun:
 
-  $ make compile
+  $ make compile SIM=true for a simulation version
       (which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
 
+  $ make compile for a synthesizable (on Xilinx) version
+      (which generates RTL and then $ cp Verilog_RTL/* xilinx_ip/hdl/)
+
+The simulation version uses simulation models for the integer divider,
+while the synthesis version uses Xilinx IP.
+
 >================================================================