diff --git a/Doc/Performance_Monitoring.md b/Doc/Performance_Monitoring.md new file mode 100644 index 0000000..e61559e --- /dev/null +++ b/Doc/Performance_Monitoring.md @@ -0,0 +1,94 @@ +# Performance Monitoring Module + +This overview is based on this [document](https://github.com/CTSRD-CHERI/Flute/blob/CHERI/Doc/Performance_Monitor/Performance_Monitoring.md). + +## Usage +To use the module, enable `PERFORMANCE_MONITORING` in your build (ensure that `BSC_COMPILATION_FLAGS` includes `-D PERFORMANCE_MONITORING` when running make). +Code running on a core with `PERFORMANCE_MONITORING` enabled can now access any of the relevant counter CSRs as specified by the [RISC-V Privileged Specification](https://riscv.org/technical/specifications/) (section __3.1.11 Hardware Performance Monitor__). +The implemented CSRs are: +- `mcycle` and `minstret` (also work without `PERFORMANCE_MONITORING` enabled) +- `mhpmcounter3–mhpmcounter31` event counters (29 total) +- `mcycleh`, `minstreth` & `mhpmcounternh` versions of the above to access the high bits on RV32 +- `cycle`, `instret` & `hpmcountern` as read-only shadows +- `mhpmevent3-mhpmevent31` event selectors +- `mcounteren` to enable reads to masked counters in S- and U-mode (Seems that check is implemented in CSR_RegFile, but never used) +- `mcountinhibit` to control which counters increment +- `scounteren` to enable reads to masked counters in U-mode + +## Events +Any event happening any number of times per cycle in the core can be counted, using the provided `mhpmcounter` and `mhpmevent` CSRs. Most common events are already provided, though it should be simple to extend and add additional events as needed. +The following events along with corresponding event id (this id should be written to the `mhpmevent` selector CSR) are given: +- No event (0x0) + +Core events: +- Redirect – count PC redirects (0x1) +- Traps – caused by a dmem exception or failed CHERI check (0x2) +- Branch – count branch instrs (0x3) +- Jal – count jal instrs (0x4) +- Jalr – count jalr instrs (0x5) +- Auipc – count auipc instrs (0x6) +- Load – count load instrs (0x7) +- Store – count store instrs (0x8) +- LR – count lr instrs (0x9) +- SC – count sc instrs (0xa) +- AMO – count (non lr or sc) atomic instrs (0xb) +- Serial shift – count serial shift (slli, srli, srai) instrs (0xc) +- Integer Mult/Div – count integer multiply and divide instrs (0xd) +- FP – count all floating point instrs (0xe) +- SC Success – count SC successes (0xf) +- Load wait – count cycles waiting on load (0x10) +- Store wait – count cycles waiting on store (0x11) +- Fence – count fence instrs (0x12) + +The following events are defined in Toooba, but not implemented (mostly due +to the fact that they are Flute-only events) + +------------------------------- + +- F Busy No Consume – count cycles where stage F is busy (0x13) +- D Busy No Consume – count cycles where stage F is ready to pipe but D is busy (0x14) +- 1 Busy No Consume – count cycles where stage D is ready to pipe but 1 is busy (0x15) +- 2 Busy No Consume – count cycles where stage 1 is ready to pipe but 2 is busy (0x16) +- 3 Busy No Consume – count cycles where stage 2 is ready to pipe but 3 is busy (0x17) +- Imprecise setbounds – count when a setbounds instr does NOT result in the exact bounds requested (0x18) +- Unrepresentable cap – count when a capability is out of bounds (due to set offset instr) and is nullified (0x19) + +--------------------------------------------------- + +- Mem cap load – count when capability wide data are loaded, regardless of tag (0x1a) +- Mem cap store – count when capability wide data are loaded, regardless of tag (0x1b) +- Mem cap load tag set – count when a tagged capability is loaded (0x1c) +- Mem cap store tag set – count when stage a tagged capability is stored (0x1d) + +IMem, DMem L1 Cache, and LL Cache; events identical for all three, though some are irrelevant for the respective caches. IDs in format (IMem/DMem/LLC): +- Load – count loads requested by cpu (0x20/0x30/unimplemented) +- Load miss – count loads missed (0x21/0x31/0x61) +- Load miss latency – count cycles waiting on a load miss (0x22/0x32/0x62) +- Store – count stores requested by cpu (unimplemented/0x33/unimplemented) +- Store miss – unimplemented +- Store miss latency – unimplemented +- Amo – count atomic ops requested by cpu (unimplemented/0x36/unimplemented) +- Amo miss – count atomics missed (unimplemented/0x37/unimplemented) +- Amo miss latency – count cycles waiting on a atomics miss (unimplemented/0x38/unimplemented) +- Tlb – count tlb accesses (0x29/0x39/unimplemented) +- Tlb miss – count tlb missed (0x2a/0x3a/unimplemented) +- Tlb miss latency – count cycles waiting on a tlb miss (0x2b/0x3b/unimplemented) +- Tlb flush – count tlb flushes (0x2c/0x3c/unimplemented) +- Evict – count cache line evictions (unimplemented/unimplemented/unimplemented) + + +TagController events: +- Load (0x70) +- Load miss (0x71) +- Write – count writes to tag cache (0x73) +- Write miss (0x74) +- Set tag write (unimplemented) +- Set tag read (unimplemented) +- Evict (0x7d) + +Missing events are: +- L1 WT CHERI events +- L1 WB events +- L2 WB events +- AXI4 events for CHERI-enabled builds +- External events \ No newline at end of file