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Merge branch 'master' into RVFI_DII, a complex merge for the fetch stage!

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Jonathan Woodruff
2020-03-18 11:35:59 +00:00
parent 1246aae7f8 c278e4fe68
commit 3a79b022ea
1059 changed files with 1467937 additions and 324026 deletions
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builds/Resources/Include_RISCY_Config.mk
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@@ -16,7 +16,7 @@ PERF_COUNT := true
# dram type in simulation: VC707 or AWSF1
SIM_DRAM_TYPE := AWSF1
# use Xilinx FPU IP cores
USE_XILINX_FPU ?= true
USE_XILINX_FPU ?= false
# default 1 core
CORE_NUM ?= 1
@@ -73,7 +73,6 @@ BSC_COMPILATION_FLAGS += \
-D CORE_$(CORE_SIZE) \
-D NUM_CORES=$(CORE_NUM) \
-D CACHE_$(CACHE_SIZE) \
-D USE_XILINX_FPU \
-D XILINX_FP_FMA_LATENCY=$(XILINX_FP_FMA_LATENCY) \
-D XILINX_INT_MUL_LATENCY=$(XILINX_INT_MUL_LATENCY) \
-D USE_BSV_BRAM_SYNC_FIFO \