From 3cdc2d31c8a479ba5c0e0826ea0ce06c5faf9e6c Mon Sep 17 00:00:00 2001
From: Jonathan Woodruff <jdw57@cam.ac.uk>
Date: Mon, 21 Mar 2022 10:13:48 +0000
Subject: [PATCH] Experimentally increase delay before reset.

---
 src_Core/RISCY_OOO/procs/lib/Ras.bsv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src_Core/RISCY_OOO/procs/lib/Ras.bsv b/src_Core/RISCY_OOO/procs/lib/Ras.bsv
index 15b72e2..5fa6905 100644
--- a/src_Core/RISCY_OOO/procs/lib/Ras.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Ras.bsv
@@ -74,7 +74,7 @@ module mkRas(ReturnAddrStack) provisos(NumAlias#(TExp#(TLog#(RasEntries)), RasEn
     Bool invalidHead = !(valids[head[0]][0]);
     Reg#(Bit#(6)) delay <- mkReg(0);
     rule resetValidHead;
-        if (delay < 10 && invalidHead) delay <= delay + 1;
+        if (delay < 32 && invalidHead) delay <= delay + 1;
         else begin
             valids[head[0]][2] <= True;
             delay <= 0;