diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
index 8b59771..b39fc2c 100755
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/AluExePipeline.bsv
@@ -226,7 +226,7 @@ interface AluExePipeline;
 endinterface
 
 module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
-    Bool verbose = True;
+    Bool verbose = False;
     Integer verbosity = 0;
 
     // alu reservation station
@@ -323,7 +323,7 @@ module mkAluExePipeline#(AluExeInput inIfc)(AluExePipeline);
             end
         end
 
-        
+
 
         else if(x.dInst.iType == CJALR || x.dInst.iType == Jr) begin
             let res_targets = inIfc.checkTarget(ppc);
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 2b76ca7..d671913 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -252,7 +252,7 @@ interface MemExePipeline;
 endinterface
 
 module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
-    Bool verbose = True;
+    Bool verbose = False;
 
     // we change cache request in case of single core, becaues our MSI protocol
     // is not good with single core