Cheri-research/Toooba
1
0
Fork 0
Code Issues 1 Pull Requests Actions Packages Projects Releases Wiki Activity

Bugfix. Now passing 'rv64mi-p-illegal' ISA test

Browse Source 
Modified:
    src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
        In getTrap() function, added check for WFI trap
	(WFI traps if MSTATUS.TW==1 and PRIV < M)
This commit is contained in:
rsnikhil
2019-04-11 12:30:14 -04:00
parent f280287589
commit 3dcb189694
2 changed files with 1961 additions and 1973 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3925
builds/RV64ADFIMSU_Toooba_verilator/Verilog_RTL/mkCore.v
View File

File diff suppressed because it is too large Load Diff

9
src_Core/RISCY_OOO/procs/RV64G_OOO/RenameStage.bsv
View File

@@ -227,6 +227,13 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
csr_access_trap = (write_deny || priv_deny); csr_access_trap = (write_deny || priv_deny);
end end
// Check WFI trap (using a time-out of 0)
Bit #(32) inst_WFI = 32'h_1050_0073;
Bit #(1) mstatus_tw = mstatus [21];
Bool wfi_trap = ( (x.inst == inst_WFI)
&& (mstatus_tw == 1'b1)
&& (csrf.decodeInfo.prv < prvM));
if (isValid(x.cause)) begin if (isValid(x.cause)) begin
// previously found exception // previously found exception
trap = tagged Valid (tagged Exception fromMaybe(?, x.cause)); trap = tagged Valid (tagged Exception fromMaybe(?, x.cause));
@@ -237,7 +244,7 @@ module mkRenameStage#(RenameInput inIfc)(RenameStage);
// newly found exception // newly found exception
trap = tagged Valid (tagged Exception fromMaybe(?, new_exception)); trap = tagged Valid (tagged Exception fromMaybe(?, new_exception));
end end
else if (fs_trap || csr_access_trap) begin else if (fs_trap || csr_access_trap || wfi_trap) begin
trap = tagged Valid (tagged Exception IllegalInst); trap = tagged Valid (tagged Exception IllegalInst);
end end
return trap; return trap;