diff --git a/builds/Resources/Include_bluesim.mk b/builds/Resources/Include_bluesim.mk
index 0ff1201..195f92b 100644
--- a/builds/Resources/Include_bluesim.mk
+++ b/builds/Resources/Include_bluesim.mk
@@ -40,6 +40,8 @@ BSC_C_FLAGS += \
 	-Xl -v \
 	-Xc -O1 -Xc++ -O1 \
 
+BSC_COMPILATION_FLAGS += \
+        -D RVFI
 
 # For Bluespec_2019.05.beta2-debian9stretch-amd64
 # you may have to remove the line: -Xc++ -D_GLIBCXX_USE_CXX11_ABI=0
diff --git a/src_Core/CPU/LLC_AXI4_Adapter.bsv b/src_Core/CPU/LLC_AXI4_Adapter.bsv
index 956ea85..1e9c6c8 100644
--- a/src_Core/CPU/LLC_AXI4_Adapter.bsv
+++ b/src_Core/CPU/LLC_AXI4_Adapter.bsv
@@ -85,7 +85,7 @@ module mkLLC_AXi4_Adapter #(MemFifoClient #(idT, childT) llc)
            );
 
    // Verbosity: 0: quiet; 1: LLC transactions; 2: loop detail
-   Integer verbosity = 2;
+   Integer verbosity = 0;
    Reg #(Bit #(4)) cfg_verbosity <- mkConfigReg (fromInteger (verbosity));
 
    // ================================================================
diff --git a/src_Core/RISCY_OOO/coherence/src/IBank.bsv b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
index 4ce0636..e98daf5 100644
--- a/src_Core/RISCY_OOO/coherence/src/IBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/IBank.bsv
@@ -145,7 +145,7 @@ module mkIBank#(
     Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
 );
 
-    Bool verbose = True;
+    Bool verbose = False;
 
     ICRqMshr#(cRqNum, wayT, tagT, procRqT, resultT) cRqMshr <- mkICRqMshrLocal;
 
@@ -770,7 +770,7 @@ module mkIBank#(
             rsToPIndexQ.enq(PRq (n));
         end
     endrule
-    
+
     rule discardPrefetchRqResult(
             cRqMshr.prefetcher.getResult(prefetchIndexQ.first) matches tagged Valid .inst);
         prefetchIndexQ.deq;
diff --git a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
index 1d20eb0..2aa44d0 100644
--- a/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/L1Bank.bsv
@@ -158,7 +158,7 @@ module mkL1Bank#(
     Add#(TAdd#(tagSz, indexSz), TAdd#(lgBankNum, LgLineSzBytes), AddrSz)
 );
 
-   Bool verbose = False;
+    Bool verbose = False;
 
     L1CRqMshr#(cRqNum, wayT, tagT, procRqT) cRqMshr <- mkL1CRqMshrLocal;
 
@@ -372,7 +372,7 @@ endfunction
         procRqT r = ProcRq {
             id: ?, //Or maybe do 0 here
             addr: addr,
-            toState: S, 
+            toState: S,
             op: Ld,
             byteEn: ?,
             data: ?,
diff --git a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv
index 10690ef..1e09fce 100644
--- a/src_Core/RISCY_OOO/coherence/src/LLBank.bsv
+++ b/src_Core/RISCY_OOO/coherence/src/LLBank.bsv
@@ -191,7 +191,7 @@ module mkLLBank#(
     Add#(TLog#(TDiv#(childNum,2)), c__, TLog#(childNum))
 );
 
-   Bool verbose = True;
+   Bool verbose = False;
 
     LLCRqMshr#(cRqNum, wayT, tagT, Vector#(childNum, DirPend), cRqT) cRqMshr <- mkLLMshr;
 
@@ -431,7 +431,7 @@ endfunction
             fromState: I,
             toState: E,
             canUpToE: True,
-            child: child, 
+            child: child,
             byteEn: ?,
             id: Child (?)
         };