diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 2976094..3ef8faf 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -480,8 +480,8 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
         let {paddr, cause} = dTlbResp.resp;
 
 `ifdef RVFI_DII
-        // TestRIG expects us throw an access fault for any memory access outside of a 64-KiB memory at 0x8000000.
-        if (!isValid(cause) && (paddr < 'h80000000 || paddr >= 'h80010000)) begin
+        // TestRIG expects us throw an access fault for any memory access outside of a 8 MiB memory at 0x8000000.
+        if (!isValid(cause) && (paddr < 'h80000000 || paddr >= 'h80800000)) begin
             case(x.mem_func)
                 Ld, Lr: begin
                     cause = Valid (LoadAccessFault);
diff --git a/src_Testbench/SoC/SoC_Map.bsv b/src_Testbench/SoC/SoC_Map.bsv
index 22f3abb..b251867 100644
--- a/src_Testbench/SoC/SoC_Map.bsv
+++ b/src_Testbench/SoC/SoC_Map.bsv
@@ -76,7 +76,7 @@ SoC_Map_Struct {
    near_mem_io_addr_base: 'h_0200_0000,
 
    main_mem_addr_base:    'h_8000_0000,
-   main_mem_addr_size:    'h_0001_0000,
+   main_mem_addr_size:    'h_0080_0000,
    pc_reset_value:        'h_8000_0000
    };
 `endif