diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
index 808a35e..361f522 100644
--- a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test.txt
@@ -4,2651 +4,580 @@ make[1]: 'elf_to_hex' is up to date.
 make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex'
 ../../Tests/elf_to_hex/elf_to_hex  ../../Tests/isa/testC  Mem.hex
 c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file
-Section .text           : addr         80000000 to addr         80000030; size 0x      30 (= 48) bytes
-Section .bss            : addr         80010000 to addr         80010800; size 0x     800 (= 2048) bytes
+Section .text           : addr         80000000 to addr         8000006a; size 0x      6a (= 106) bytes
 Section .riscv.attributes: Ignored
 Section .comment        : Ignored
 Section .symtab         : Searching for addresses of '_start', 'exit' and 'tohost' symbols
 Writing symbols to:    symbol_table.txt
+    No 'exit' label found
     No 'tohost' symbol found
 Section .shstrtab       : Ignored
 Section .strtab         : Ignored
 Min addr:                    80000000 (hex)
-Max addr:                    800107ff (hex)
+Max addr:                    80000069 (hex)
 Writing mem hex to file 'Mem.hex'
 Subtracting 0x80000000 base from addresses
 ./exe_HW_sim  +v1  +tohost
-Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 2112 to 33554430.
+Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 4 to 33554430.
 1: top.soc_top.rl_reset_start_initial ...
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 11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
   SoC address map:
   Boot ROM:        0x1000 .. 0x2000
   Mem0 Controller: 0x80000000 .. 0xc0000000
   UART0:           0xc0000000 .. 0xc0000080
 11: top.soc_top.rl_reset_complete_initial
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 ================================================================
 Bluespec RISC-V standalone system simulation v1.2
 Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
 ================================================================
 INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0
 12: top.soc_top.method start (tohost 0, fromhost 0)
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 100: top.soc_top.rl_step_0, n = 0, do_release
 100: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
 100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
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 101: top.soc_top.rl_ctrl_req
 101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
 101: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
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   [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
   [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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 [RFile] wr_          1: r 40 <= 0000000000000400000000001fffff44000000
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 [RFile] wr_          0: r 41 <= 0000000000000408000000001fffff44000000
 instret:0  PC:0x1ffff0000000000000000000000001000  instr:0x00000297   iType:Auipc    [doCommitNormalInst [0]]        167
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 instret:1  PC:0x1ffff0000000000000000000000001004  instr:0x02028593   iType:Alu    [doCommitNormalInst [0]]        168
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   [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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 [RFile] wr_          0: r 42 <= 0000000000000000000000001fffff44000000
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 instret:2  PC:0x1ffff0000000000000000000000001008  instr:0xf1402573   iType:Csr    [doCommitSystemInst]        224
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   [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
   [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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                 3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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                 3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
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                 3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
 Decoded delta = 0
 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False }
-incrementing TLB counter
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 Received delta = 0
                 3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
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 [doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True  >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, loadTags: False }
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-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
 [RFile] wr_          3: r 43 <= 0000000020000000000000001fffff44000000
 [doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000  > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000  > }
-[stats] enabled 1
-calling cycle
 instret:3  PC:0x1ffff000000000000000000000000100c  instr:0x0182b283   iType:Ld    [doCommitNormalInst [0]]        403
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
 [ALU redirect -           1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
-[stats] enabled 1
-calling cycle
 [ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02  > ; <V 'h02 'h02  > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h1 ; <V 'h03 'h02  > ; <V 'h00 'h00  >
-[stats] enabled 1
-calling cycle
 instret:4  PC:0x1ffff0000000000000000000000001010  instr:0x00028067   iType:Jr    [doCommitNormalInst [0]]        408
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
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-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h40001000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h46, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
   [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipcc, execFunc: tagged Alu Add, capFunc: tagged CapModify tagged SpecialRW tagged TCC , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrPCC, imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
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-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h48, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
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-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged ModifyOffset IncOffset, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000a }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h07}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h49, src2: tagged Valid 'h4a, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
-[stats] enabled 1
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-[RFile] wr_          0: r 46 <= 0000000000020000000000001fffff44000000
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h05, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h47, src2: tagged Valid 'h45, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h48, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h46, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h47, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h02, rn2 'h06}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h48, src2: tagged Valid 'h49, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffff800 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h49, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000012 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4b, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 46 <= 0000000010000400000000001fffff44000000
 [RFile] wr_          1: r 45 <= 40000000200000000000ffff1fffff44000000
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapInspect GetBase, capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
-  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
-[stats] enabled 1
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-[RFile] wr_          1: r 47 <= 0000000000020000400000001fffff44000000
-instret:5  PC:0x1ffff0000000000000000000080000000  instr:0x020002db   iType:Auipcc    [doCommitNormalInst [0]]       1155
-instret:6  PC:0x1ffff0000000000000000000080000004  instr:0x000802b7   iType:Alu    [doCommitNormalInst [1]]       1155
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-[RFile] wr_          0: r 48 <= 0000000020000400000000001fffff44000000
-instret:7  PC:0x1ffff0000000000000000000080000008  instr:0x00002285   iType:Alu    [doCommitNormalInst [0]]       1156
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-[RFile] wr_          0: r 4a <= 0000000000000002000000001fffff44000000
-[RFile] wr_          1: r 49 <= 0000000020000400000000001fffff44000000
-               11570 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-instret:8  PC:0x1ffff000000000000000000008000000a  instr:0x000002b2   iType:Alu    [doCommitNormalInst [0]]       1157
-[stats] enabled 1
-calling cycle
-[RFile] wr_          1: r 4b <= 0000000020000400100000001ffff804021000
-               11580 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h4c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
-               11580 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-instret:9  PC:0x1ffff000000000000000000008000000c  instr:0x2052815b   iType:Cap    [doCommitNormalInst [0]]       1158
-instret:10  PC:0x1ffff0000000000000000000080000010  instr:0x000043a1   iType:Alu    [doCommitNormalInst [1]]       1158
-[stats] enabled 1
-calling cycle
-[RFile] wr_          0: r 4c <= 0000014020000400100000001ffff804021000
-[RFile] wr_          1: r 4f <= 0000000000000000400000001fffff44000000
-               11590 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000050080001000 o: 'h0000050080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
-Decoded delta = 10
+[RFile] wr_          1: r 47 <= 0000000020000800000000001fffff44000000
+instret:5  PC:0x1ffff0000000000000000000080000000  instr:0x0200055b   iType:Auipcc    [doCommitNormalInst [0]]       1155
+instret:6  PC:0x1ffff0000000000000000000080000004  instr:0x400012b7   iType:Alu    [doCommitNormalInst [1]]       1155
+[RFile] wr_          0: r 48 <= 40000000200008000000ffff1fffff44000000
+[RFile] wr_          1: r 49 <= 3ffffffffffffe000fff00001fffff44000000
+instret:7  PC:0x1ffff0000000000000000000080000008  instr:0x00000286   iType:Alu    [doCommitNormalInst [0]]       1156
+[RFile] wr_          0: r 4a <= 00000000200008000000ffff1fffff44020000
+[RFile] wr_          1: r 4b <= 0000000020000005800000001fffff44000000
+instret:8  PC:0x1ffff000000000000000000008000000a  instr:0x2055015b   iType:Cap    [doCommitNormalInst [0]]       1157
+instret:9  PC:0x1ffff000000000000000000008000000e  instr:0x80000313   iType:Alu    [doCommitNormalInst [1]]       1157
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h08, src2: tagged Valid 'h4d, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h001, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          0: r 4c <= 0000000020000007800000001fffff44000000
+[ALU redirect -           0] 'h1ffff0000000000000000000080000028; 'h0; InstTag { way: 'h0, ptr: 'h06, t: 'h0c }
+instret:10  PC:0x1ffff0000000000000000000080000012  instr:0x1061015b   iType:Cap    [doCommitNormalInst [0]]       1158
+instret:11  PC:0x1ffff0000000000000000000080000016  instr:0x00000097   iType:Auipc    [doCommitNormalInst [1]]       1158
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h06, t: 'h0c } ; 'h1 ; 'h0 ; <V 'h08 'h07  > ; <V 'h06 'h06  > ; <V <V False False False False False False True True False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False True False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h1 ; <V 'h07 'h06  > ; <V 'h01 'h01  >
+instret:12  PC:0x1ffff000000000000000000008000001a  instr:0x012080e7   iType:Jr    [doCommitNormalInst [0]]       1160
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h4d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h50, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               12130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h51, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+               12140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h4c, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12140 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h53, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h54, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 4d <= 00000000200007f0000000001fffff44000000
+               12150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000001e o: 'h000000008000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff8, write: True, capStore: False, potentialCapLoad: False }
+               12150 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Valid 'h08, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h1, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12150 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h55, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h56, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h54, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h55, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 50 <= 0000000020000800000000001fffff44000000
+Received delta = 0
+               12160 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff8, check_high: 'h00000000080002000, check_inclusive: True } }, specBits: 'h000 }
+               12160 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h1, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff0, write: True, capStore: False, potentialCapLoad: False }
+               12160 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:13  PC:0x1ffff0000000000000000000080000028  instr:0x00007139   iType:Alu    [doCommitNormalInst [0]]       1216
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h56, src2: tagged Valid 'h53, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h57, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          0: r 51 <= 0000000000000000000000001fffff44000000
+Received delta = 0
+               12170 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h1, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff0, check_high: 'h00000000080001ff8, check_inclusive: True } }, specBits: 'h000 }
+               12170 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fec o: 'h0000000080001fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False  >, shiftBEData: <V False False False False False False False False False False False False True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fec, write: True, capStore: False, potentialCapLoad: False }
+instret:14  PC:0x1ffff000000000000000000008000002a  instr:0x0000fc06   iType:St    [doCommitNormalInst [0]]       1217
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 53 <= 40000000000000000000ffff1fffff44000000
+[RFile] wr_          1: r 54 <= 0000000000020000000000001fffff44000000
+Received delta = 0
+               12180 : [doFinishMem] DTlbResp { resp: <'h0000000080001fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, ldstq_tag: tagged St 'h2, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True  >, vaddr: v: True a: 'h0000000080001fec o: 'h0000000080001fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fec, check_high: 'h00000000080001ff0, check_inclusive: True } }, specBits: 'h000 }
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001ff8, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True  >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802a }
+               12180 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               12180 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
+instret:15  PC:0x1ffff000000000000000000008000002c  instr:0x0000f822   iType:St    [doCommitNormalInst [0]]       1218
+instret:16  PC:0x1ffff000000000000000000008000002e  instr:0x00000080   iType:Alu    [doCommitNormalInst [1]]       1218
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          1: r 55 <= 0000000000020000400000001fffff44000000
+               12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
+               12190 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+               12190 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12190 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:17  PC:0x1ffff0000000000000000000080000030  instr:0x00004501   iType:Alu    [doCommitNormalInst [0]]       1219
+instret:18  PC:0x1ffff0000000000000000000080000032  instr:0xfea42623   iType:St    [doCommitNormalInst [1]]       1219
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 56 <= 0000000020000400000000001fffff44000000
+               12200 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               12200 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h57, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12200 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:19  PC:0x1ffff0000000000000000000080000036  instr:0x021005db   iType:Cap    [doCommitNormalInst [0]]       1220
+instret:20  PC:0x1ffff000000000000000000008000003a  instr:0x00080637   iType:Alu    [doCommitNormalInst [1]]       1220
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               12210 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001ff8, fromState: I, toState: M, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
+[RFile] wr_          1: r 57 <= 40000000200004000000ffff1fffff44000000
+Received delta = 0
+               12210 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               12210 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h804a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               12210 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: True, capStore: True, potentialCapLoad: True }
+               12210 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12210 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+instret:21  PC:0x1ffff000000000000000000008000003e  instr:0x00002605   iType:Alu    [doCommitNormalInst [0]]       1221
+instret:22  PC:0x1ffff0000000000000000000080000040  instr:0x00000632   iType:Alu    [doCommitNormalInst [1]]       1221
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+Received delta = 0
+               12220 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, ldstq_tag: tagged St 'h3, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               12220 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               12220 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: I, dir: , owner: tagged Valid 'h0, other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               12220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               12220 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by other cRq 'h0, depend on cRq tagged Valid 'h0
+instret:23  PC:0x1ffff0000000000000000000080000042  instr:0x20c585db   iType:Cap    [doCommitNormalInst [0]]       1222
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               12230 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               12230 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h8056 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+               12230 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:24  PC:0x1ffff0000000000000000000080000046  instr:0xfcb44823   iType:St    [doCommitNormalInst [0]]       1223
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               12240 : [doRespLdForward] 'h02; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+[RFile] wr_          3: r 5c <= 40000000200004000000ffff1fffff44000000
+               12240 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               12240 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               12250 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff8, write: False, capStore: False, potentialCapLoad: False }
+               12250 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 }
+               12250 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               12260 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff8, check_high: 'h00000000080002000, check_inclusive: True } }, specBits: 'h000 }
+               12260 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001ff8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > } }
+               12260 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False }
-incrementing TLB counter
-               11590 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h01, src2: tagged Valid 'h4f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
-instret:11  PC:0x1ffff0000000000000000000080000012  instr:0x1071015b   iType:Cap    [doCommitNormalInst [0]]       1159
-[stats] enabled 1
-calling cycle
-[RFile] wr_          1: r 4d <= 0000014020000400000000001fffff44000000
-Received delta = 10
-               11600 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, ldstq_tag: tagged Ld 'h01, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h000000a, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
-               11600 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h01, paddr: 'h000000008000100a, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h801e } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
-               11600 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h01, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+               12260 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+[RFile] wr_          0: r 61 <= 0000000020000800000000001fffff44000000
+Received delta = 0
+               12270 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h0b, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
+               12270 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h805a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               12270 : [doRespLdForward] 'h04; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000001e 'h0000000000000000  > } }
+[RFile] wr_          3: r 5f <= 0000000020000007800000001fffff44000000
+               12270 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff0, write: False, capStore: False, potentialCapLoad: False }
+               12270 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+Received delta = 0
+               12280 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff0, check_high: 'h00000000080001ff8, check_inclusive: True } }, specBits: 'h000 }
+               12280 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001ff0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h8064 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+               12280 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h2, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               12280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               12280 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
+               12290 : [doRespLdForward] 'h05; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+[RFile] wr_          3: r 60 <= 0000000000000000000000001fffff44000000
+               12300 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h0000000080001000, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
+               13480 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001ff8, toState: M, child: , data: tagged Valid CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > }, id: 'h0 }
+               13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h0, other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h00, addr: 'h0000000080001ff8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802a }
+[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V False False False False False False False False True True True True True True True True  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > } }
+               13490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h000000008000001e  >  > } ; tagged Valid 'h1
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001ff0, isMMIO: False, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h802c }
+               13500 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Valid 'h1, other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               13500 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: own by itself, hit
+               13500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h01, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               13500 : [Ld resp] 'h01; TaggedData { tag: True, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }
+               13500 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h000000008000001e  >  > } ; tagged Invalid 
+               13500 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802c }
+               13510 : [doRespLdMem] 'h01; TaggedData { tag: True, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > } }
+[RFile] wr_          3: r 59 <= 6aaaaaaaaaaaaaaaaaaaaaaad555566eaa2aa8
+               13510 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802c }
+               13510 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               13510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h00, addr: 'h0000000080001ff0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h802c }
+[Store resp] idx 'h00, WaitStResp { offset: 'h3, shiftedBE: <V True True True True True True True True False False False False False False False False  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+               13510 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080001fd0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, fault: tagged Invalid , allowCap: True, killed: tagged Valid St }
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001fec, isMMIO: False, shiftedBE: <V False False False False False False False False False False False False True True True True  >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8032 }
+               13520 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               13520 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
+               13530 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
+               13530 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               13530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h00, addr: 'h0000000080001fec, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8032 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h2, shiftedBE: <V False False False False False False False False False False False False True True True True  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+               13530 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+               13530 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001fd0, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True  >, stData: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8046 }
+               13540 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8046 }
+               13550 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               13550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8046 }
+               13550 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               13550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8046 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True True True True True True True True True  >, shiftedData: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+               13550 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h59, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               14060 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+               14070 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               14080 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               14080 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+Received delta = 0
+               14090 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, ldstq_tag: tagged Ld 'h02, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14090 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h02, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h804a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14090 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h03, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14090 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+               14100 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h03, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               14100 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               14100 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h02, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               14100 : [Ld resp] 'h02; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False } }
+               14100 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               14110 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h03, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14110 : [doRespLdMem] 'h02; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+[RFile] wr_          3: r 59 <= 40000000200004000000ffff1fffff44000000
+               14110 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h61, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h02, instTag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h59, isFpuReg: False }, paddr: 'h0000000080001fd0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid  }
+               14120 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h05, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14120 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h5f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h04, t: 'h09 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               14130 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h05, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff8, write: False, capStore: False, potentialCapLoad: False }
+               14130 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5a, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14130 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:25  PC:0x1ffff000000000000000000008000004a  instr:0xfd04258f   iType:Ld    [doCommitNormalInst [0]]       1413
+[RFile] wr_          1: r 5a <= 40000000200004001000ffff1ffff804021000
+Received delta = 0
+               14140 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, ldstq_tag: tagged Ld 'h05, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff8, check_high: 'h00000000080002000, check_inclusive: True } }, specBits: 'h000 }
+               14140 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h05, paddr: 'h0000000080001ff8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14140 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001000 o: 'h0000000000000000 b: 'h0000000080001000 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: True, capStore: True, potentialCapLoad: True }
+               14140 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h4d, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14140 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080001ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 }
+[RFile] wr_          0: r 61 <= 0000000020000800000000001fffff44000000
+Received delta = 0
+               14150 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, ldstq_tag: tagged St 'h4, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14150 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff0, write: False, capStore: False, potentialCapLoad: False }
+               14150 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080001ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 }
+               14150 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h05, addr: 'h0000000080001ff8, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8062 }
+               14150 : [Ld resp] 'h05; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False } }
+               14150 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+instret:26  PC:0x1ffff000000000000000000008000004e  instr:0x0085a5db   iType:Cap    [doCommitNormalInst [0]]       1415
+Received delta = 0
+               14160 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, ldstq_tag: tagged Ld 'h06, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff0, check_high: 'h00000000080001ff8, check_inclusive: True } }, specBits: 'h000 }
+               14160 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h06, paddr: 'h0000000080001ff0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h8064 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14160 : [doRespLdMem] 'h05; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000001e 'h0000000000000000  > } }
+[RFile] wr_          3: r 5f <= 0000000020000007800000001fffff44000000
+               14160 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 }
+instret:27  PC:0x1ffff0000000000000000000080000052  instr:0xfcb44823   iType:St    [doCommitNormalInst [0]]       1416
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001fd0, isMMIO: False, shiftedBE: <V True True True True True True True True True True True True True True True True  >, stData: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > }, allowCapAmoLd: True, fault: tagged Invalid , pcHash: 'h8052 }
+               14170 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 }
+               14170 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h06, addr: 'h0000000080001ff0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8064 }
+               14170 : [Ld resp] 'h06; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False } }
+               14170 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+               14170 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8052 }
+               14180 : [doRespLdMem] 'h06; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+[RFile] wr_          3: r 60 <= 0000000000000000000000001fffff44000000
+               14180 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h1, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000000000000  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8052 }
+               14180 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h1 ; ProcRq { id: 'h00, addr: 'h0000000080001fd0, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8052 }
+[Store resp] idx 'h00, WaitStResp { offset: 'h1, shiftedBE: <V True True True True True True True True True True True True True True True True  >, shiftedData: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > } }
+               14180 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+[ALU redirect -           0] 'h1ffff000000000000000000008000001e; 'h0; InstTag { way: 'h1, ptr: 'h04, t: 'h09 }
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h04, t: 'h09 } ; 'h0 ; 'h1 ; <V 'h05 'h05  > ; <V 'h02 'h01  > ; <V <V False False True True True False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False True True True True False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h0 ; <V 'h05 'h05  > ; <V 'h00 'h00  >
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h64, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h05, t: 'h0b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h51, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h63, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h65, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h61, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h67, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+               14290 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h08, t: 'h11 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 64 <= 0000000000000000000000001fffff44000000
+[RFile] wr_          1: r 63 <= 0000000000000000000000001fffff44000000
+               14300 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h64, src2: tagged Valid 'h65, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14300 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h09, t: 'h12 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+               14310 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h0000000080001000, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > }, id: 'h0 }
+[RFile] wr_          1: r 65 <= 0000000000000000400000001fffff44000000
+               14310 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000000, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, rVal1: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000001 o: 'h0000000000000001 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
 Decoded delta = 0
 DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000000000, write: True, capStore: False, potentialCapLoad: False }
-incrementing TLB counter
-               11600 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
-instret:12  PC:0x1ffff0000000000000000000080000016  instr:0x00a1115b   iType:Cap    [doCommitNormalInst [0]]       1160
-[stats] enabled 1
-calling cycle
+               14310 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h5f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14310 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000030, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h10}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00080000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0a, t: 'h15 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SpecialRW tagged Normal , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Valid scrAddrDDC, imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 67 <= 00000000200007f0000000001fffff44000000
 Received delta = 0
-               11610 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
-               11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h0, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000000000, cs: I, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False True  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
-               11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
-               11610 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, miss no replace
-instret:13  PC:0x1ffff000000000000000000008000001a  instr:0xfe210e5b   iType:Cap    [doCommitNormalInst [0]]       1161
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-               11630 L1 top.soc_top.corew_proc.core_0 sendRqToP: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e } ; L1CRqSlot { way: 'h0, cs: I, repTag: 'h2aaaaaaaaaaaa, waitP: True } ; CRqMsg { addr: 'h000000008000100a, fromState: I, toState: E, canUpToE: True, id: 'h0, child: , isPrefetchRq: False }
-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-[stats] enabled 1
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-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0a, t: 'h14 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h001, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h002, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h003, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h007, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h15, t: 'h2a }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h16, t: 'h2c }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h17, t: 'h2e }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h18, t: 'h30 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h19, t: 'h32 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1a, t: 'h34 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1b, t: 'h36 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1c, t: 'h38 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1d, t: 'h3a }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1e, t: 'h3c }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h1f, t: 'h3e }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-               12370 L1 top.soc_top.corew_proc.core_0 pRsTransfer: PRsMsg { addr: 'h000000008000100a, toState: E, child: , data: tagged Valid CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > }, id: 'h0 }
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-               12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h0, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } }, repInfo: , setAuxData: tagged Invalid  }
-               12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
-               12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h0 ; ProcRq { id: 'h01, addr: 'h000000008000100a, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h801e }
-               12380 : [Ld resp] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False } }
-               12380 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  > <V 'h0000000000000000 'h0000000000000000  >  > } ; tagged Invalid 
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, spec_bits: 'h00f, spec_tag: tagged Valid 'h4, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-               12390 : [doRespLdMem] 'h01; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
-[RFile] wr_          3: r 4e <= 0000000000000000000000001fffff44000000
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h04, t: 'h08 }, spec_bits: 'h01d, spec_tag: tagged Valid 'h1, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h01, instTag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h4e, isFpuReg: False }, paddr: 'h000000008000100a, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h05, t: 'h0a }, spec_bits: 'h01e, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-instret:14  PC:0x1ffff000000000000000000008000001e  instr:0x00006282   iType:Ld    [doCommitNormalInst [0]]       1241
-instret:15  PC:0x1ffff0000000000000000000080000020  instr:0x00004305   iType:Alu    [doCommitNormalInst [1]]       1241
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h06, t: 'h0c }, spec_bits: 'h01b, spec_tag: tagged Valid 'h2, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: J, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h1f, rn2 'h1f, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hfffffffc }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h07, t: 'h0e }, spec_bits: 'h017, spec_tag: tagged Valid 'h3, regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
-[stats] enabled 1
-calling cycle
-[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8022 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False  >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, loadTags: False }
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-[stats] enabled 1
-calling cycle
-1247: mmioPlatform.rl_tohost: 0x1 (= 1)
+               14320 : [doFinishMem] DTlbResp { resp: <'h0000000000000000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, ldstq_tag: tagged St 'h6, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000000000, check_high: 'h00000000000000008, check_inclusive: True } }, specBits: 'h000 }
+               14320 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000038, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h000000008000001e o: 'h000000008000001e b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff8, write: True, capStore: False, potentialCapLoad: False }
+               14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1PRs , way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Valid 'h2, other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: pRs: 
+               14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h2 ; ProcRq { id: 'h03, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               14320 : [Ld resp] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQHitInfo { waitWPResp: True, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }
+               14320 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } ; tagged Invalid 
+               14320 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Valid 'h60, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14320 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffec, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Sll, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h0000000c }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6f, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h70, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0b, t: 'h17 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Addw, capFunc: tagged Other , capChecks: CapChecks {rn1 'h0c, rn2 'h0c}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h6e, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h6f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0b, t: 'h16 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 6a <= 0000000020000800000000001fffff44000000
+Received delta = 0
+               14330 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h07, t: 'h0f }, ldstq_tag: tagged St 'h7, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff8, check_high: 'h00000000080002000, check_inclusive: True } }, specBits: 'h000 }
+               14330 : [doRespLdMem] 'h03; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQRespLdResult { wrongPath: True, dst: tagged Invalid , allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > } }
+               14330 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'h00000030, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h08, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff0, write: True, capStore: False, potentialCapLoad: False }
+               14330 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffec, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h9, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetAddr Src1Addr, capChecks: CapChecks {rn1 'h0c, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h70, src2: tagged Valid 'h6d, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h71, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0c, t: 'h18 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          0: r 6b <= 0000000000000000000000001fffff44000000
+Received delta = 0
+               14340 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h08, t: 'h10 }, ldstq_tag: tagged St 'h8, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff0, check_high: 'h00000000080001ff8, check_inclusive: True } }, specBits: 'h000 }
+               14340 : [doIssueLd] fromIssueQ: True ; LSQIssueLdInfo { tag: 'h03, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h8056 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14340 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffec, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h9, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fec o: 'h0000000080001fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0a, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True False False False False False False False False False False False False  >, shiftBEData: <V False False False False False False False False False False False False True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fec, write: True, capStore: False, potentialCapLoad: False }
+               14340 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Cap, execFunc: tagged Other , capFunc: tagged CapModify tagged SetBounds SetBoundsRounding, capChecks: CapChecks {rn1 'h0b, rn2 'h0b}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000008 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h73, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h74, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0d, t: 'h1b }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 6e <= 0000000000020000000000001fffff44000000
+[RFile] wr_          1: r 6d <= 40000000000000000000ffff1fffff44000000
+Received delta = 0
+               14350 : [doFinishMem] DTlbResp { resp: <'h0000000080001fec,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h09, t: 'h13 }, ldstq_tag: tagged St 'h9, shiftedBE: tagged DataMemAccess <V False False False False False False False False False False False False True True True True  >, vaddr: v: True a: 'h0000000080001fec o: 'h0000000080001fec b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fec, check_high: 'h00000000080001ff0, check_inclusive: True } }, specBits: 'h000 }
+               14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h3, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 }
+               14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h3 ; ProcRq { id: 'h03, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h8056 }
+               14350 : [Ld resp] 'h03; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False } }
+               14350 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+               14350 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+[RFile] wr_          1: r 6f <= 0000000000020000400000001fffff44000000
+               14360 : [doRespLdMem] 'h03; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > } }
+[RFile] wr_          3: r 5c <= 40000000200004001000ffff1ffff804021000
+               14360 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14360 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 70 <= 0000000020000400000000001fffff44000000
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h03, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5c, isFpuReg: False }, paddr: 'h0000000080001fd0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, fault: tagged Invalid , allowCap: True, killed: tagged Invalid  }
+               14370 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               14370 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h5c, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 }
+               14370 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 71 <= 40000000200004000000ffff1fffff44000000
+Received delta = 0
+               14380 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0d, t: 'h1a }, ldstq_tag: tagged Ld 'h07, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14380 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h07, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h804a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14380 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, rVal1: v: True a: 'h0000000080001000 o: 'h0000000000000000 b: 'h0000000080001000 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000000000000 b: 'h0000000080001000 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False }
+               14380 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h71, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14380 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'hffffffd0, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+               14380 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+instret:28  PC:0x1ffff0000000000000000000080000056  instr:0xfd04258f   iType:Ld    [doCommitNormalInst [0]]       1438
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+Received delta = 0
+               14390 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, ldstq_tag: tagged Ld 'h04, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000000000000 b: 'h0000000080001000 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000080001000, authority_top: 'h00000000080001008, authority_idx: 'h0b, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
+               14390 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h04, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h805a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14390 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: True, capStore: True, potentialCapLoad: True }
+               14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h4, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h4 ; ProcRq { id: 'h07, addr: 'h0000000080001fd0, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h804a }
+               14390 : [Ld resp] 'h07; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False } }
+               14390 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+               14390 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14390 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               14400 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0c, t: 'h19 }, ldstq_tag: tagged St 'ha, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14400 : [doRespLdMem] 'h07; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h73, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000004039004  > } }
+[RFile] wr_          3: r 73 <= 40000000200004001000ffff1ffff804021000
+               14400 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'hffffffd0, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h10, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: False, capStore: False, potentialCapLoad: True }
+               14400 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h5, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               14400 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h5 ; ProcRq { id: 'h04, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               14400 : [Ld resp] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False } }
+               14400 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } ; tagged Invalid 
+               14400 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000038, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000040 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'he } }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h11, t: 'h22 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               14410 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h0e, t: 'h1d }, ldstq_tag: tagged Ld 'h08, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14410 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h08, paddr: 'h0000000080001fd0, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, pcHash: 'h8056 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+               14410 : [doRespLdMem] 'h04; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000  > } }
+[RFile] wr_          3: r 5d <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
+               14410 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000038, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14410 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h01, rn2 'h01, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h79, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h11, t: 'h23 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h04, instTag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5d, isFpuReg: False }, paddr: 'h0000000080001000, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }
+               14420 : [doRespLdForward] 'h08; TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h76, isFpuReg: False }, allowCap: True, data: TaggedData { tag: True, data: <V 'h0000000080001000 'hffff000000000000  > } }
+[RFile] wr_          3: r 76 <= 40000000200004000000ffff1fffff44000000
+               14420 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000038, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff8, write: False, capStore: False, potentialCapLoad: False }
+               14420 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h50, src2: tagged Valid 'h5d, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14420 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffd0, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 74 <= 40000000200004001000ffff1ffff804021000
+Received delta = 0
+               14430 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h10, t: 'h20 }, ldstq_tag: tagged Ld 'h0a, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001ff8 o: 'h0000000080001ff8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff8, check_high: 'h00000000080002000, check_inclusive: True } }, specBits: 'h000 }
+               14430 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0a, paddr: 'h0000000080001ff8, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, pcHash: 'h8062 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > } }
+               14430 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'haaaaaaaaaaaaaaaa o: 'haaaaaaaaaaaaaaaa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fc8 o: 'h0000000080001fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fc8, write: True, capStore: False, potentialCapLoad: False }
+               14430 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffd0, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h74, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+               14430 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000000, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:29  PC:0x1ffff000000000000000000008000005a  instr:0xfab585db   iType:Ld    [doCommitNormalInst [0]]       1443
+[RFile] wr_          0: r 7b <= 0000000020000800000000001fffff44000000
+Received delta = 0
+               14440 : [doFinishMem] DTlbResp { resp: <'h0000000080001fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, ldstq_tag: tagged St 'h5, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fc8 o: 'h0000000080001fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fc8, check_high: 'h00000000080001fd0, check_inclusive: True } }, specBits: 'h000 }
+               14440 : [doRespLdForward] 'h0a; TaggedData { tag: False, data: <V 'h0000000000000000 'h000000008000001e  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h79, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h000000008000001e 'h0000000000000000  > } }
+[RFile] wr_          3: r 79 <= 0000000020000007800000001fffff44000000
+               14440 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffd0, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: True a: 'h0000000080001000 o: 'h0000000000000000 b: 'h0000000080001000 t: 'h00000000080001008 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, shiftBEData: <V True True True True True True True True True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fd0, write: True, capStore: True, potentialCapLoad: True }
+               14440 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000000, regs: PhyRegs { src1: tagged Valid 'h76, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: False }, spec_bits: 'h000 }
+               14440 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000030, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+Received delta = 0
+               14450 : [doFinishMem] DTlbResp { resp: <'h0000000080001fd0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h0, ptr: 'h0e, t: 'h1c }, ldstq_tag: tagged St 'hb, shiftedBE: tagged DataMemAccess <V True True True True True True True True True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fd0 o: 'h0000000080001fd0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: True, allowCapLoad: True, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fd0, check_high: 'h00000000080001fe0, check_inclusive: True } }, specBits: 'h000 }
+               14450 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000000, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, rVal1: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h0b, rn2 'h0b, bounds check: auth Src1, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001000, write: False, capStore: False, potentialCapLoad: False }
+               14450 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000030, regs: PhyRegs { src1: tagged Valid 'h67, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0b, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:30  PC:0x1ffff000000000000000000008000005e  instr:0xfcb43423   iType:St    [doCommitNormalInst [0]]       1445
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h05, instTag: InstTag { way: 'h0, ptr: 'h03, t: 'h06 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h5f, isFpuReg: False }, paddr: 'h0000000080001ff8, isMMIO: False, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }
+Received delta = 0
+               14460 : [doFinishMem] DTlbResp { resp: <'h0000000080001000,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h0, ptr: 'h0f, t: 'h1e }, ldstq_tag: tagged Ld 'h09, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001000 o: 'h0000000080001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h0b, check_low: 'h0000000080001000, check_high: 'h00000000080001008, check_inclusive: True } }, specBits: 'h000 }
+[doDeqStQ_St] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000080001fc8, isMMIO: False, shiftedBE: <V False False False False False False False False True True True True True True True True  >, stData: TaggedData { tag: False, data: <V 'h0000000000000000 'haaaaaaaaaaaaaaaa  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h805e }
+               14460 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h09, paddr: 'h0000000080001000, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h805a } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged ToCache 
+               14460 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000030, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0b, rVal1: v: True a: 'h0000000080001fc0 o: 'h0000000080001fc0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h02, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V True True True True True True True True False False False False False False False False  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001ff0, write: False, capStore: False, potentialCapLoad: False }
+               14460 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+[doDeqLdQ_Ld] LdQDeqEntry { tag: 'h06, instTag: InstTag { way: 'h1, ptr: 'h03, t: 'h07 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h60, isFpuReg: False }, paddr: 'h0000000080001ff0, isMMIO: False, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }
+[ALU redirect -           0] 'h1ffff000000000000000000008000001e; 'h0; InstTag { way: 'h1, ptr: 'h11, t: 'h23 }
+Received delta = 0
+               14470 : [doFinishMem] DTlbResp { resp: <'h0000000080001ff0,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h10, t: 'h21 }, ldstq_tag: tagged Ld 'h0b, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, vaddr: v: True a: 'h0000000080001ff0 o: 'h0000000080001ff0 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001ff0, check_high: 'h00000000080001ff8, check_inclusive: True } }, specBits: 'h000 }
+               14470 : [doIssueLd] fromIssueQ: False ; LSQIssueLdInfo { tag: 'h0b, paddr: 'h0000000080001ff0, shiftedBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, pcHash: 'h8064 } ; SBSearchRes { matchIdx: tagged Invalid , forwardData: tagged Invalid  } ; tagged Forward LSQForwardResult { dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+               14470 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h6, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: E, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               14470 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h6 ; ProcRq { id: 'h09, addr: 'h0000000080001000, toState: E, op: Ld, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805a }
+               14470 : [Ld resp] 'h09; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQHitInfo { waitWPResp: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False } }
+               14470 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False False False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  >  > } ; tagged Invalid 
+               14470 L1 top.soc_top.corew_proc.core_0 cRqTransfer_new: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e }
+instret:31  PC:0x1ffff0000000000000000000080000062  instr:0x000070e2   iType:Ld    [doCommitNormalInst [0]]       1447
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h1, ptr: 'h11, t: 'h23 } ; 'h0 ; 'h1 ; <V 'h12 'h12  > ; <V 'h04 'h03  > ; <V <V False False False False True True True True True True True True True True True True True True False False False False False False False False False False False False False False  > <V False False False True True True True True True True True True True True True True True True False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h0 ; <V 'h12 'h12  > ; <V 'h00 'h00  >
+               14490 : [doRespLdMem] 'h09; TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h77, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'h0000000000000000  > } }
+[RFile] wr_          3: r 77 <= 2aaaaaaaaaaaaaaa8aaa00001fffff44000000
+               14490 L1 top.soc_top.corew_proc.core_0 pipelineResp: PipeOut { cmd: tagged L1CRq 'h7, way: 'h0, pRqMiss: False, ram: RamData { info: CacheInfo { tag: 'h0000000040000, cs: M, dir: , owner: tagged Invalid , other:  }, line: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } }, repInfo: , setAuxData: tagged Invalid  }
+               14490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e }
+               14490 L1 top.soc_top.corew_proc.core_0 pipelineResp: cRq: no owner, hit
+               14490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: 'h7 ; ProcRq { id: 'h00, addr: 'h0000000080001fc8, toState: M, op: St, byteEn: <V False True False True False True False True False True False True False True False True  >, data: TaggedData { tag: False, data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, amoInst: AmoInst { func: None, width: Word, aq: True, rl: False }, loadTags: False, pcHash: 'h805e }
+[Store resp] idx 'h00, WaitStResp { offset: 'h0, shiftedBE: <V False False False False False False False False True True True True True True True True  >, shiftedData: TaggedData { tag: False, data: <V 'h0000000000000000 'haaaaaaaaaaaaaaaa  > } }
+               14490 L1 top.soc_top.corew_proc.core_0 pipelineResp: Hit func: update ram: CLine { tag: <V False True False False  >, data: <V <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > <V 'h0000000080001000 'hffff000004039004  > <V 'haaaaaaaaaaaaaaaa 'h00000000aaaaaaaa  > <V 'h0000000000000000 'h000000008000001e  >  > } ; tagged Invalid 
+               14490 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: St, imm: 'hffffffc8, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+instret:32  PC:0x1ffff0000000000000000000080000064  instr:0x00007442   iType:Ld    [doCommitNormalInst [0]]       1449
+instret:33  PC:0x1ffff0000000000000000000080000066  instr:0x00006121   iType:Alu    [doCommitNormalInst [1]]       1449
+               14500 : [doRespLdForward] 'h0b; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > }; LSQRespLdResult { wrongPath: False, dst: tagged Valid PhyDst { indx: 'h7a, isFpuReg: False }, allowCap: False, data: TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000000000000  > } }
+[RFile] wr_          3: r 7a <= 0000000000000000000000001fffff44000000
+               14500 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: St, imm: 'hffffffc8, regs: PhyRegs { src1: tagged Valid 'h6a, src2: tagged Valid 'h77, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+instret:34  PC:0x1ffff0000000000000000000080000068  instr:0x00008082   iType:Jr    [doCommitNormalInst [0]]       1450
+instret:35  PC:0x1ffff000000000000000000008000001e  instr:0x0000832a   iType:Alu    [doCommitNormalInst [1]]       1450
+               14510 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: St, imm: 'hffffffc8, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, rVal1: v: True a: 'h0000000080002000 o: 'h0000000080002000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'haaaaaaaaaaaaaaaa o: 'haaaaaaaaaaaaaaaa b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000080001fc8 o: 'h0000000080001fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h08, rn2 'h0b, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000080001fc8, write: True, capStore: False, potentialCapLoad: False }
+instret:36  PC:0x1ffff0000000000000000000080000020  instr:0x00004281   iType:Alu    [doCommitNormalInst [0]]       1451
+instret:37  PC:0x1ffff0000000000000000000080000022  instr:0x00004305   iType:Alu    [doCommitNormalInst [1]]       1451
+Received delta = 0
+               14520 : [doFinishMem] DTlbResp { resp: <'h0000000080001fc8,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: St, tag: InstTag { way: 'h1, ptr: 'h0f, t: 'h1f }, ldstq_tag: tagged St 'hc, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000080001fc8 o: 'h0000000080001fc8 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000080001fc8, check_high: 'h00000000080001fd0, check_inclusive: True } }, specBits: 'h000 }
+[doDeqStQ_MMIO_issue] StQDeqEntry { instTag: InstTag { way: 'h1, ptr: 'h06, t: 'h0d }, memFunc: St, amoFunc: None, acq: False, rel: False, dst: tagged Invalid , paddr: 'h0000000000000000, isMMIO: True, shiftedBE: <V True True True True True True True True False False False False False False False False  >, stData: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, allowCapAmoLd: False, fault: tagged Invalid , pcHash: 'h8024 }; MMIOCRq { addr: 'h0000000000000000, func: tagged St , byteEn: <V True True True True True True True True False False False False False False False False  >, data: TaggedData { tag: False, data: <V 'h0000000000000001 'h0000000000000000  > }, loadTags: False }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7e, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h12, t: 'h25 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h0a}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Valid 'h6b, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7d, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h12, t: 'h24 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000001 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h00, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h7f, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h13, t: 'h26 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000000, ldstq_tag: tagged St 'hd, cap_checks: CapChecks {rn1 'h05, rn2 'h06, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h7e, src2: tagged Valid 'h7f, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h13, t: 'h27 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: False, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffc0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hd } }, regs: PhyRegs { src1: tagged Valid 'h7b, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h0b, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h14, t: 'h28 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: St, imm: 'h00000038, ldstq_tag: tagged St 'h0, cap_checks: CapChecks {rn1 'h02, rn2 'h01, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h0b, src2: tagged Valid 'h79, src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h1, ptr: 'h14, t: 'h29 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+1457: mmioPlatform.rl_tohost: 0x1 (= 1)
 PASS
diff --git a/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt
new file mode 100644
index 0000000..31140ee
--- /dev/null
+++ b/builds/RV64ACDFIMSUxCHERI_Toooba_bluesim/test1.txt
@@ -0,0 +1,1621 @@
+make -C  ../../Tests/elf_to_hex
+make[1]: Entering directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex'
+make[1]: 'elf_to_hex' is up to date.
+make[1]: Leaving directory '/Users/akilan/Documents/Cheri/Test/Reverse/Test/TooobaTest/Toooba/Tests/elf_to_hex'
+../../Tests/elf_to_hex/elf_to_hex  ../../Tests/isa/testC  Mem.hex
+c_mem_load_elf: ../../Tests/isa/testC is a 64-bit ELF file
+Section .text           : addr         80000000 to addr         80000010; size 0x      10 (= 16) bytes
+Section .comment        : Ignored
+Section .riscv.attributes: Ignored
+Section .symtab         : Searching for addresses of '_start', 'exit' and 'tohost' symbols
+Writing symbols to:    symbol_table.txt
+    No 'exit' label found
+    No 'tohost' symbol found
+Section .shstrtab       : Ignored
+Section .strtab         : Ignored
+Min addr:                    80000000 (hex)
+Max addr:                    8000000f (hex)
+Writing mem hex to file 'Mem.hex'
+Subtracting 0x80000000 base from addresses
+./exe_HW_sim  +v1  +tohost
+Warning: file 'Mem.hex' for memory 'rf' has a gap at addresses 1 to 33554430.
+1: top.soc_top.rl_reset_start_initial ...
+11: Mem_Controller.set_addr_map: addr_base 0x80000000 addr_lim 0xc0000000
+  SoC address map:
+  Boot ROM:        0x1000 .. 0x2000
+  Mem0 Controller: 0x80000000 .. 0xc0000000
+  UART0:           0xc0000000 .. 0xc0000080
+11: top.soc_top.rl_reset_complete_initial
+================================================================
+Bluespec RISC-V standalone system simulation v1.2
+Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.
+================================================================
+INFO: watch_tohost 1, tohost_addr = 0x0, fromhost_addr = 0x0
+12: top.soc_top.method start (tohost 0, fromhost 0)
+100: top.soc_top.rl_step_0, n = 0, do_release
+100: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
+100: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
+101: top.soc_top.rl_ctrl_req
+101: top.soc_top.corew_proc.method start: startpc 1000, tohostAddr 0, fromhostAddr 0
+101: top.soc_top do_release(restartRunning: True, to_host_addr: 0)
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000020 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h41, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h00, t: 'h01 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Auipc, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h40, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h00, t: 'h00 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 40 <= 0000000000000400000000001fffff44000000
+[RFile] wr_          0: r 41 <= 0000000000000408000000001fffff44000000
+instret:0  PC:0x1ffff0000000000000000000000001000  instr:0x00000297   iType:Auipc    [doCommitNormalInst [0]]        167
+instret:1  PC:0x1ffff0000000000000000000000001004  instr:0x02028593   iType:Alu    [doCommitNormalInst [0]]        168
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Csr, execFunc: tagged Alu Csrs, capFunc: tagged Other , capChecks: CapChecks {rn1 'h00, rn2 'h00}, csr: tagged Valid csrAddrMHARTID, scr: tagged Invalid , imm: tagged Invalid  }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'h0 } }, regs: PhyRegs { src1: tagged Invalid , src2: tagged Valid 'h00, src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h42, isFpuReg: False } }, tag: InstTag { way: 'h0, ptr: 'h01, t: 'h02 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          0: r 42 <= 0000000000000000000000001fffff44000000
+instret:2  PC:0x1ffff0000000000000000000000001008  instr:0xf1402573   iType:Csr    [doCommitSystemInst]        224
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Jr, execFunc: tagged Br AT, capFunc: tagged Other , capChecks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Pcc, low Src1Addr, high Src1AddrPlus2, inclusive True}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'h00000000 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h43, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Invalid  }, tag: InstTag { way: 'h0, ptr: 'h02, t: 'h04 }, spec_bits: 'h000, spec_tag: tagged Valid 'h0, regs_ready: RegsReady { src1: False, src2: True, src3: True, dst: True } }
+  [mkReservationStationRow::_write] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+                3340 : [doDispatchMem] ToReservationStation { data: MemRSData { mem_func: Ld, imm: 'h00000018, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+                3350 : [doRegReadMem] ToSpecFifo { data: MemDispatchToRegRead { mem_func: Ld, imm: 'h00000018, regs: PhyRegs { src1: tagged Valid 'h40, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, ddc_offset: True }, spec_bits: 'h000 }
+                3360 : [doExeAndDoMem] ToSpecFifo { data: MemRegReadToExe { mem_func: Ld, imm: 'h00000018, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, rVal1: v: True a: 'h0000000000001000 o: 'h0000000000001000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, rVal2: v: False a: 'h0000000000000000 o: 'h0000000000000000 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h0000 hp: 'h000 ot: 'h3ffff f: 'h0, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, cap_checks: CapChecks {rn1 'h05, rn2 'h05, bounds check: auth Ddc, low Vaddr, high VaddrPlusSize, inclusive True}, origBE: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, shiftBEData: <V False False False False False False False False True True True True True True True True  > }, spec_bits: 'h000 }
+Decoded delta = 0
+DTLB top.soc_top.corew_proc.core_0.coreFix_memExe_dTlb req (bare): TlbReq { addr: 'h0000000000001018, write: False, capStore: False, potentialCapLoad: False }
+Received delta = 0
+                3370 : [doFinishMem] DTlbResp { resp: <'h0000000000001018,tagged Invalid ,True>, inst: MemExeToFinish { mem_func: Ld, tag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, ldstq_tag: tagged Ld 'h00, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, vaddr: v: True a: 'h0000000000001018 o: 'h0000000000001018 b: 'h0000000000000000 t: 'h10000000000000000 sp: 'h000f hp: 'hfff ot: 'h3ffff f: 'h0, delta: 'h0000000, misaligned: False, capStore: False, allowCapLoad: False, capException: tagged Invalid , check: tagged Valid BoundsCheck { authority_base: 'h0000000000000000, authority_top: 'h10000000000000000, authority_idx: 'h21, check_low: 'h0000000000001018, check_high: 'h00000000000001020, check_inclusive: True } }, specBits: 'h000 }
+[doDeqLdQ_MMIO_issue] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; MMIOCRq { addr: 'h0000000000001018, func: tagged Ld , byteEn: <V False False False False False False False False True True True True True True True True  >, data: TaggedData { tag: , data: <V 'haaaaaaaaaaaaaaaa 'haaaaaaaaaaaaaaaa  > }, loadTags: False }
+[RFile] wr_          3: r 43 <= 0000000020000000000000001fffff44000000
+[doDeqLdQ_MMIO_deq] LdQDeqEntry { tag: 'h00, instTag: InstTag { way: 'h1, ptr: 'h01, t: 'h03 }, memFunc: Ld, byteOrTagEn: tagged DataMemAccess <V True True True True True True True True False False False False False False False False  >, unsignedLd: False, acq: False, rel: False, dst: tagged Valid PhyDst { indx: 'h43, isFpuReg: False }, paddr: 'h0000000000001018, isMMIO: True, shiftedBE: tagged DataMemAccess <V False False False False False False False False True True True True True True True True  >, fault: tagged Invalid , allowCap: False, killed: tagged Invalid  }; TaggedData { tag: False, data: <V 'h0000000000000000 'h0000000080000000  > }; TaggedData { tag: False, data: <V 'h0000000080000000 'h0000000000000000  > }
+instret:3  PC:0x1ffff000000000000000000000000100c  instr:0x0182b283   iType:Ld    [doCommitNormalInst [0]]        403
+[ALU redirect -           1] 'h1ffff0000000000000000000080000000; 'h0; InstTag { way: 'h0, ptr: 'h02, t: 'h04 }
+[ROB incorrectSpec] 'h0 ; InstTag { way: 'h0, ptr: 'h02, t: 'h04 } ; 'h1 ; 'h0 ; <V 'h03 'h02  > ; <V 'h02 'h02  > ; <V <V False False True False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; <V <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  > <V False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False False  >  > ; 'h1 ; <V 'h03 'h02  > ; <V 'h00 'h00  >
+instret:4  PC:0x1ffff0000000000000000000000001010  instr:0x00028067   iType:Jr    [doCommitNormalInst [0]]        408
+  [mkReservationStationRow::_write] ToReservationStation { data: AluRSData { dInst: DecodedInst { iType: Alu, execFunc: tagged Alu Add, capFunc: tagged Other , capChecks: CapChecks {rn1 'h02, rn2 'h02}, csr: tagged Invalid , scr: tagged Invalid , imm: tagged Valid 'hffffffe0 }, trainInfo: PredTrainInfo { dir: TourTrainInfo { globalHist: 'haaa, localHist: 'h2aa, globalTaken: True, localTaken: False, pcIndex: 'h2aa }, ras: 'hf } }, regs: PhyRegs { src1: tagged Valid 'h02, src2: tagged Invalid , src3: tagged Invalid , dst: tagged Valid PhyDst { indx: 'h45, isFpuReg: False } }, tag: InstTag { way: 'h1, ptr: 'h02, t: 'h05 }, spec_bits: 'h000, spec_tag: tagged Invalid , regs_ready: RegsReady { src1: True, src2: True, src3: True, dst: True } }
+[RFile] wr_          1: r 45 <= 3ffffffffffffff80fff00001fffff44000000
+instret:5  PC:0x1ffff0000000000000000000080000000  instr:0x0000713d   iType:Alu    [doCommitNormalInst [0]]       1155
+instret:6  PC:0x1ffff0000000000000000000080000002  instr:0x0000a806  iType:St    [doCommitTrap]       1157
+instret:7  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1166
+instret:8  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1175
+instret:9  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1184
+instret:10  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1193
+instret:11  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1202
+instret:12  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1211
+instret:13  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1220
+instret:14  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1229
+instret:15  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1238
+instret:16  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1247
+instret:17  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1256
+instret:18  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1265
+instret:19  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1274
+instret:20  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1283
+instret:21  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1292
+instret:22  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1301
+instret:23  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1310
+instret:24  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1319
+instret:25  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1328
+instret:26  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1337
+instret:27  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1346
+instret:28  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1355
+instret:29  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1364
+instret:30  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1373
+instret:31  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1382
+instret:32  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1391
+instret:33  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1400
+instret:34  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1409
+instret:35  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1418
+instret:36  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1427
+instret:37  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1436
+instret:38  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1445
+instret:39  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1454
+instret:40  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1463
+instret:41  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1472
+instret:42  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1481
+instret:43  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1490
+instret:44  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1499
+instret:45  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1508
+instret:46  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1517
+instret:47  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1526
+instret:48  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1535
+instret:49  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1544
+instret:50  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1553
+instret:51  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1562
+instret:52  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1571
+instret:53  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1580
+instret:54  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1589
+instret:55  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1598
+instret:56  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1607
+instret:57  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1616
+instret:58  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1625
+instret:59  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1634
+instret:60  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1643
+instret:61  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1652
+instret:62  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1661
+instret:63  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1670
+instret:64  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1679
+instret:65  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1688
+instret:66  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1697
+instret:67  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1706
+instret:68  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1715
+instret:69  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1724
+instret:70  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1733
+instret:71  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1742
+instret:72  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1751
+instret:73  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1760
+instret:74  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1769
+instret:75  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1778
+instret:76  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1787
+instret:77  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1796
+instret:78  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1805
+instret:79  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1814
+instret:80  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1823
+instret:81  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1832
+instret:82  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1841
+instret:83  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1850
+instret:84  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1859
+instret:85  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1868
+instret:86  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1877
+instret:87  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1886
+instret:88  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1895
+instret:89  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1904
+instret:90  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1913
+instret:91  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1922
+instret:92  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1931
+instret:93  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1940
+instret:94  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1949
+instret:95  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1958
+instret:96  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1967
+instret:97  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1976
+instret:98  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1985
+instret:99  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       1994
+instret:100  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2003
+instret:101  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2012
+instret:102  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2021
+instret:103  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2030
+instret:104  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2039
+instret:105  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2048
+instret:106  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2057
+instret:107  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2066
+instret:108  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2075
+instret:109  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2084
+instret:110  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2093
+instret:111  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2102
+instret:112  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2111
+instret:113  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2120
+instret:114  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2129
+instret:115  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2138
+instret:116  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2147
+instret:117  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2156
+instret:118  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2165
+instret:119  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2174
+instret:120  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2183
+instret:121  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2192
+instret:122  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2201
+instret:123  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2210
+instret:124  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2219
+instret:125  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2228
+instret:126  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2237
+instret:127  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2246
+instret:128  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2255
+instret:129  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2264
+instret:130  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2273
+instret:131  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2282
+instret:132  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2291
+instret:133  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2300
+instret:134  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2309
+instret:135  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2318
+instret:136  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2327
+instret:137  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2336
+instret:138  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2345
+instret:139  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2354
+instret:140  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2363
+instret:141  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2372
+instret:142  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2381
+instret:143  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2390
+instret:144  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2399
+instret:145  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2408
+instret:146  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2417
+instret:147  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2426
+instret:148  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2435
+instret:149  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2444
+instret:150  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2453
+instret:151  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2462
+instret:152  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2471
+instret:153  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2480
+instret:154  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2489
+instret:155  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2498
+instret:156  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2507
+instret:157  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2516
+instret:158  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2525
+instret:159  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2534
+instret:160  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2543
+instret:161  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2552
+instret:162  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2561
+instret:163  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2570
+instret:164  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2579
+instret:165  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2588
+instret:166  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2597
+instret:167  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2606
+instret:168  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2615
+instret:169  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2624
+instret:170  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2633
+instret:171  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2642
+instret:172  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2651
+instret:173  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2660
+instret:174  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2669
+instret:175  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2678
+instret:176  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2687
+instret:177  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2696
+instret:178  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2705
+instret:179  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2714
+instret:180  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2723
+instret:181  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2732
+instret:182  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2741
+instret:183  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2750
+instret:184  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2759
+instret:185  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2768
+instret:186  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2777
+instret:187  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2786
+instret:188  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2795
+instret:189  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2804
+instret:190  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2813
+instret:191  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2822
+instret:192  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2831
+instret:193  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2840
+instret:194  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2849
+instret:195  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2858
+instret:196  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2867
+instret:197  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2876
+instret:198  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2885
+instret:199  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2894
+instret:200  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2903
+instret:201  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2912
+instret:202  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2921
+instret:203  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2930
+instret:204  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2939
+instret:205  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2948
+instret:206  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2957
+instret:207  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2966
+instret:208  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2975
+instret:209  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2984
+instret:210  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       2993
+instret:211  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3002
+instret:212  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3011
+instret:213  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3020
+instret:214  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3029
+instret:215  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3038
+instret:216  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3047
+instret:217  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3056
+instret:218  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3065
+instret:219  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3074
+instret:220  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3083
+instret:221  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3092
+instret:222  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3101
+instret:223  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3110
+instret:224  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3119
+instret:225  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3128
+instret:226  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3137
+instret:227  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3146
+instret:228  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3155
+instret:229  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3164
+instret:230  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3173
+instret:231  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3182
+instret:232  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3191
+instret:233  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3200
+instret:234  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3209
+instret:235  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3218
+instret:236  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3227
+instret:237  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3236
+instret:238  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3245
+instret:239  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3254
+instret:240  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3263
+instret:241  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3272
+instret:242  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3281
+instret:243  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3290
+instret:244  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3299
+instret:245  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3308
+instret:246  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3317
+instret:247  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3326
+instret:248  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3335
+instret:249  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3344
+instret:250  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3353
+instret:251  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3362
+instret:252  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3371
+instret:253  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3380
+instret:254  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3389
+instret:255  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3398
+instret:256  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3407
+instret:257  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3416
+instret:258  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3425
+instret:259  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3434
+instret:260  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3443
+instret:261  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3452
+instret:262  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3461
+instret:263  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3470
+instret:264  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3479
+instret:265  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3488
+instret:266  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3497
+instret:267  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3506
+instret:268  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3515
+instret:269  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3524
+instret:270  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3533
+instret:271  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3542
+instret:272  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3551
+instret:273  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3560
+instret:274  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3569
+instret:275  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3578
+instret:276  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3587
+instret:277  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3596
+instret:278  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3605
+instret:279  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3614
+instret:280  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3623
+instret:281  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3632
+instret:282  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3641
+instret:283  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3650
+instret:284  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3659
+instret:285  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3668
+instret:286  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3677
+instret:287  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3686
+instret:288  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3695
+instret:289  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3704
+instret:290  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3713
+instret:291  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3722
+instret:292  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3731
+instret:293  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3740
+instret:294  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3749
+instret:295  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3758
+instret:296  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3767
+instret:297  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3776
+instret:298  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3785
+instret:299  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3794
+instret:300  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3803
+instret:301  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3812
+instret:302  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3821
+instret:303  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3830
+instret:304  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3839
+instret:305  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3848
+instret:306  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3857
+instret:307  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3866
+instret:308  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3875
+instret:309  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3884
+instret:310  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3893
+instret:311  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3902
+instret:312  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3911
+instret:313  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3920
+instret:314  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3929
+instret:315  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3938
+instret:316  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3947
+instret:317  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3956
+instret:318  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3965
+instret:319  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3974
+instret:320  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3983
+instret:321  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       3992
+instret:322  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4001
+instret:323  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4010
+instret:324  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4019
+instret:325  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4028
+instret:326  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4037
+instret:327  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4046
+instret:328  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4055
+instret:329  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4064
+instret:330  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4073
+instret:331  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4082
+instret:332  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4091
+instret:333  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4100
+instret:334  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4109
+instret:335  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4118
+instret:336  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4127
+instret:337  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4136
+instret:338  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4145
+instret:339  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4154
+instret:340  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4163
+instret:341  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4172
+instret:342  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4181
+instret:343  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4190
+instret:344  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4199
+instret:345  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4208
+instret:346  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4217
+instret:347  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4226
+instret:348  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4235
+instret:349  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4244
+instret:350  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4253
+instret:351  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4262
+instret:352  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4271
+instret:353  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4280
+instret:354  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4289
+instret:355  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4298
+instret:356  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4307
+instret:357  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4316
+instret:358  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4325
+instret:359  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4334
+instret:360  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4343
+instret:361  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4352
+instret:362  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4361
+instret:363  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4370
+instret:364  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4379
+instret:365  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4388
+instret:366  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4397
+instret:367  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4406
+instret:368  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4415
+instret:369  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4424
+instret:370  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4433
+instret:371  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4442
+instret:372  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4451
+instret:373  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4460
+instret:374  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4469
+instret:375  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4478
+instret:376  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4487
+instret:377  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4496
+instret:378  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4505
+instret:379  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4514
+instret:380  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4523
+instret:381  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4532
+instret:382  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4541
+instret:383  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4550
+instret:384  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4559
+instret:385  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4568
+instret:386  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4577
+instret:387  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4586
+instret:388  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4595
+instret:389  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4604
+instret:390  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4613
+instret:391  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4622
+instret:392  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4631
+instret:393  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4640
+instret:394  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4649
+instret:395  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4658
+instret:396  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4667
+instret:397  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4676
+instret:398  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4685
+instret:399  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4694
+instret:400  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4703
+instret:401  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4712
+instret:402  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4721
+instret:403  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4730
+instret:404  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4739
+instret:405  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4748
+instret:406  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4757
+instret:407  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4766
+instret:408  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4775
+instret:409  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4784
+instret:410  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4793
+instret:411  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4802
+instret:412  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4811
+instret:413  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4820
+instret:414  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4829
+instret:415  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4838
+instret:416  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4847
+instret:417  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4856
+instret:418  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4865
+instret:419  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4874
+instret:420  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4883
+instret:421  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4892
+instret:422  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4901
+instret:423  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4910
+instret:424  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4919
+instret:425  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4928
+instret:426  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4937
+instret:427  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4946
+instret:428  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4955
+instret:429  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4964
+instret:430  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4973
+instret:431  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4982
+instret:432  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       4991
+instret:433  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5000
+instret:434  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5009
+instret:435  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5018
+instret:436  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5027
+instret:437  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5036
+instret:438  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5045
+instret:439  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5054
+instret:440  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5063
+instret:441  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5072
+instret:442  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5081
+instret:443  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5090
+instret:444  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5099
+instret:445  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5108
+instret:446  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5117
+instret:447  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5126
+instret:448  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5135
+instret:449  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5144
+instret:450  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5153
+instret:451  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5162
+instret:452  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5171
+instret:453  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5180
+instret:454  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5189
+instret:455  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5198
+instret:456  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5207
+instret:457  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5216
+instret:458  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5225
+instret:459  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5234
+instret:460  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5243
+instret:461  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5252
+instret:462  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5261
+instret:463  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5270
+instret:464  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5279
+instret:465  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5288
+instret:466  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5297
+instret:467  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5306
+instret:468  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5315
+instret:469  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5324
+instret:470  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5333
+instret:471  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5342
+instret:472  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5351
+instret:473  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5360
+instret:474  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5369
+instret:475  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5378
+instret:476  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5387
+instret:477  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5396
+instret:478  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5405
+instret:479  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5414
+instret:480  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5423
+instret:481  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5432
+instret:482  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5441
+instret:483  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5450
+instret:484  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5459
+instret:485  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5468
+instret:486  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5477
+instret:487  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5486
+instret:488  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5495
+instret:489  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5504
+instret:490  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5513
+instret:491  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5522
+instret:492  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5531
+instret:493  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5540
+instret:494  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5549
+instret:495  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5558
+instret:496  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5567
+instret:497  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5576
+instret:498  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5585
+instret:499  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5594
+instret:500  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5603
+instret:501  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5612
+instret:502  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5621
+instret:503  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5630
+instret:504  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5639
+instret:505  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5648
+instret:506  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5657
+instret:507  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5666
+instret:508  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5675
+instret:509  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5684
+instret:510  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5693
+instret:511  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5702
+instret:512  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5711
+instret:513  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5720
+instret:514  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5729
+instret:515  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5738
+instret:516  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5747
+instret:517  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5756
+instret:518  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5765
+instret:519  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5774
+instret:520  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5783
+instret:521  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5792
+instret:522  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5801
+instret:523  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5810
+instret:524  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5819
+instret:525  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5828
+instret:526  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5837
+instret:527  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5846
+instret:528  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5855
+instret:529  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5864
+instret:530  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5873
+instret:531  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5882
+instret:532  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5891
+instret:533  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5900
+instret:534  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5909
+instret:535  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5918
+instret:536  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5927
+instret:537  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5936
+instret:538  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5945
+instret:539  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5954
+instret:540  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5963
+instret:541  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5972
+instret:542  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5981
+instret:543  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5990
+instret:544  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       5999
+instret:545  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6008
+instret:546  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6017
+instret:547  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6026
+instret:548  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6035
+instret:549  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6044
+instret:550  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6053
+instret:551  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6062
+instret:552  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6071
+instret:553  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6080
+instret:554  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6089
+instret:555  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6098
+instret:556  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6107
+instret:557  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6116
+instret:558  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6125
+instret:559  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6134
+instret:560  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6143
+instret:561  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6152
+instret:562  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6161
+instret:563  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6170
+instret:564  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6179
+instret:565  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6188
+instret:566  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6197
+instret:567  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6206
+instret:568  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6215
+instret:569  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6224
+instret:570  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6233
+instret:571  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6242
+instret:572  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6251
+instret:573  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6260
+instret:574  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6269
+instret:575  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6278
+instret:576  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6287
+instret:577  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6296
+instret:578  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6305
+instret:579  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6314
+instret:580  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6323
+instret:581  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6332
+instret:582  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6341
+instret:583  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6350
+instret:584  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6359
+instret:585  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6368
+instret:586  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6377
+instret:587  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6386
+instret:588  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6395
+instret:589  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6404
+instret:590  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6413
+instret:591  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6422
+instret:592  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6431
+instret:593  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6440
+instret:594  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6449
+instret:595  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6458
+instret:596  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6467
+instret:597  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6476
+instret:598  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6485
+instret:599  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6494
+instret:600  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6503
+instret:601  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6512
+instret:602  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6521
+instret:603  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6530
+instret:604  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6539
+instret:605  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6548
+instret:606  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6557
+instret:607  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6566
+instret:608  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6575
+instret:609  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6584
+instret:610  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6593
+instret:611  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6602
+instret:612  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6611
+instret:613  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6620
+instret:614  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6629
+instret:615  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6638
+instret:616  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6647
+instret:617  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6656
+instret:618  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6665
+instret:619  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6674
+instret:620  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6683
+instret:621  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6692
+instret:622  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6701
+instret:623  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6710
+instret:624  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6719
+instret:625  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6728
+instret:626  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6737
+instret:627  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6746
+instret:628  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6755
+instret:629  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6764
+instret:630  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6773
+instret:631  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6782
+instret:632  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6791
+instret:633  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6800
+instret:634  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6809
+instret:635  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6818
+instret:636  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6827
+instret:637  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6836
+instret:638  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6845
+instret:639  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6854
+instret:640  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6863
+instret:641  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6872
+instret:642  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6881
+instret:643  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6890
+instret:644  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6899
+instret:645  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6908
+instret:646  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6917
+instret:647  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6926
+instret:648  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6935
+instret:649  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6944
+instret:650  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6953
+instret:651  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6962
+instret:652  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6971
+instret:653  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6980
+instret:654  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6989
+instret:655  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       6998
+instret:656  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7007
+instret:657  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7016
+instret:658  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7025
+instret:659  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7034
+instret:660  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7043
+instret:661  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7052
+instret:662  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7061
+instret:663  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7070
+instret:664  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7079
+instret:665  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7088
+instret:666  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7097
+instret:667  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7106
+instret:668  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7115
+instret:669  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7124
+instret:670  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7133
+instret:671  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7142
+instret:672  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7151
+instret:673  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7160
+instret:674  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7169
+instret:675  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7178
+instret:676  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7187
+instret:677  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7196
+instret:678  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7205
+instret:679  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7214
+instret:680  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7223
+instret:681  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7232
+instret:682  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7241
+instret:683  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7250
+instret:684  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7259
+instret:685  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7268
+instret:686  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7277
+instret:687  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7286
+instret:688  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7295
+instret:689  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7304
+instret:690  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7313
+instret:691  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7322
+instret:692  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7331
+instret:693  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7340
+instret:694  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7349
+instret:695  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7358
+instret:696  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7367
+instret:697  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7376
+instret:698  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7385
+instret:699  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7394
+instret:700  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7403
+instret:701  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7412
+instret:702  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7421
+instret:703  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7430
+instret:704  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7439
+instret:705  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7448
+instret:706  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7457
+instret:707  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7466
+instret:708  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7475
+instret:709  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7484
+instret:710  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7493
+instret:711  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7502
+instret:712  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7511
+instret:713  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7520
+instret:714  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7529
+instret:715  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7538
+instret:716  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7547
+instret:717  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7556
+instret:718  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7565
+instret:719  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7574
+instret:720  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7583
+instret:721  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7592
+instret:722  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7601
+instret:723  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7610
+instret:724  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7619
+instret:725  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7628
+instret:726  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7637
+instret:727  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7646
+instret:728  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7655
+instret:729  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7664
+instret:730  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7673
+instret:731  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7682
+instret:732  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7691
+instret:733  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7700
+instret:734  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7709
+instret:735  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7718
+instret:736  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7727
+instret:737  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7736
+instret:738  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7745
+instret:739  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7754
+instret:740  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7763
+instret:741  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7772
+instret:742  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7781
+instret:743  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7790
+instret:744  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7799
+instret:745  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7808
+instret:746  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7817
+instret:747  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7826
+instret:748  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7835
+instret:749  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7844
+instret:750  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7853
+instret:751  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7862
+instret:752  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7871
+instret:753  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7880
+instret:754  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7889
+instret:755  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7898
+instret:756  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7907
+instret:757  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7916
+instret:758  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7925
+instret:759  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7934
+instret:760  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7943
+instret:761  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7952
+instret:762  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7961
+instret:763  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7970
+instret:764  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7979
+instret:765  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7988
+instret:766  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       7997
+instret:767  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8006
+instret:768  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8015
+instret:769  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8024
+instret:770  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8033
+instret:771  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8042
+instret:772  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8051
+instret:773  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8060
+instret:774  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8069
+instret:775  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8078
+instret:776  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8087
+instret:777  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8096
+instret:778  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8105
+instret:779  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8114
+instret:780  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8123
+instret:781  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8132
+instret:782  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8141
+instret:783  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8150
+instret:784  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8159
+instret:785  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8168
+instret:786  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8177
+instret:787  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8186
+instret:788  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8195
+instret:789  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8204
+instret:790  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8213
+instret:791  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8222
+instret:792  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8231
+instret:793  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8240
+instret:794  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8249
+instret:795  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8258
+instret:796  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8267
+instret:797  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8276
+instret:798  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8285
+instret:799  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8294
+instret:800  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8303
+instret:801  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8312
+instret:802  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8321
+instret:803  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8330
+instret:804  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8339
+instret:805  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8348
+instret:806  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8357
+instret:807  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8366
+instret:808  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8375
+instret:809  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8384
+instret:810  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8393
+instret:811  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8402
+instret:812  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8411
+instret:813  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8420
+instret:814  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8429
+instret:815  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8438
+instret:816  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8447
+instret:817  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8456
+instret:818  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8465
+instret:819  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8474
+instret:820  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8483
+instret:821  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8492
+instret:822  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8501
+instret:823  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8510
+instret:824  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8519
+instret:825  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8528
+instret:826  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8537
+instret:827  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8546
+instret:828  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8555
+instret:829  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8564
+instret:830  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8573
+instret:831  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8582
+instret:832  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8591
+instret:833  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8600
+instret:834  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8609
+instret:835  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8618
+instret:836  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8627
+instret:837  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8636
+instret:838  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8645
+instret:839  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8654
+instret:840  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8663
+instret:841  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8672
+instret:842  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8681
+instret:843  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8690
+instret:844  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8699
+instret:845  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8708
+instret:846  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8717
+instret:847  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8726
+instret:848  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8735
+instret:849  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8744
+instret:850  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8753
+instret:851  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8762
+instret:852  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8771
+instret:853  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8780
+instret:854  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8789
+instret:855  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8798
+instret:856  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8807
+instret:857  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8816
+instret:858  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8825
+instret:859  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8834
+instret:860  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8843
+instret:861  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8852
+instret:862  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8861
+instret:863  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8870
+instret:864  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8879
+instret:865  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8888
+instret:866  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8897
+instret:867  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8906
+instret:868  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8915
+instret:869  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8924
+instret:870  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8933
+instret:871  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8942
+instret:872  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8951
+instret:873  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8960
+instret:874  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8969
+instret:875  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8978
+instret:876  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8987
+instret:877  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       8996
+instret:878  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9005
+instret:879  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9014
+instret:880  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9023
+instret:881  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9032
+instret:882  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9041
+instret:883  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9050
+instret:884  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9059
+instret:885  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9068
+instret:886  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9077
+instret:887  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9086
+instret:888  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9095
+instret:889  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9104
+instret:890  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9113
+instret:891  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9122
+instret:892  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9131
+instret:893  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9140
+instret:894  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9149
+instret:895  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9158
+instret:896  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9167
+instret:897  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9176
+instret:898  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9185
+instret:899  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9194
+instret:900  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9203
+instret:901  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9212
+instret:902  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9221
+instret:903  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9230
+instret:904  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9239
+instret:905  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9248
+instret:906  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9257
+instret:907  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9266
+instret:908  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9275
+instret:909  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9284
+instret:910  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9293
+instret:911  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9302
+instret:912  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9311
+instret:913  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9320
+instret:914  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9329
+instret:915  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9338
+instret:916  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9347
+instret:917  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9356
+instret:918  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9365
+instret:919  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9374
+instret:920  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9383
+instret:921  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9392
+instret:922  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9401
+instret:923  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9410
+instret:924  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9419
+instret:925  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9428
+instret:926  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9437
+instret:927  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9446
+instret:928  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9455
+instret:929  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9464
+instret:930  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9473
+instret:931  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9482
+instret:932  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9491
+instret:933  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9500
+instret:934  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9509
+instret:935  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9518
+instret:936  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9527
+instret:937  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9536
+instret:938  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9545
+instret:939  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9554
+instret:940  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9563
+instret:941  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9572
+instret:942  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9581
+instret:943  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9590
+instret:944  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9599
+instret:945  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9608
+instret:946  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9617
+instret:947  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9626
+instret:948  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9635
+instret:949  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9644
+instret:950  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9653
+instret:951  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9662
+instret:952  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9671
+instret:953  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9680
+instret:954  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9689
+instret:955  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9698
+instret:956  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9707
+instret:957  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9716
+instret:958  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9725
+instret:959  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9734
+instret:960  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9743
+instret:961  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9752
+instret:962  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9761
+instret:963  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9770
+instret:964  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9779
+instret:965  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9788
+instret:966  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9797
+instret:967  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9806
+instret:968  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9815
+instret:969  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9824
+instret:970  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9833
+instret:971  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9842
+instret:972  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9851
+instret:973  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9860
+instret:974  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9869
+instret:975  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9878
+instret:976  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9887
+instret:977  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9896
+instret:978  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9905
+instret:979  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9914
+instret:980  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9923
+instret:981  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9932
+instret:982  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9941
+instret:983  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9950
+instret:984  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9959
+instret:985  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9968
+instret:986  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9977
+instret:987  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9986
+instret:988  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]       9995
+instret:989  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10004
+instret:990  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10013
+instret:991  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10022
+instret:992  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10031
+instret:993  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10040
+instret:994  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10049
+instret:995  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10058
+instret:996  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10067
+instret:997  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10076
+instret:998  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10085
+instret:999  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10094
+instret:1000  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10103
+instret:1001  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10112
+instret:1002  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10121
+instret:1003  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10130
+instret:1004  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10139
+instret:1005  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10148
+instret:1006  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10157
+instret:1007  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10166
+instret:1008  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10175
+instret:1009  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10184
+instret:1010  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10193
+instret:1011  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10202
+instret:1012  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10211
+instret:1013  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10220
+instret:1014  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10229
+instret:1015  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10238
+instret:1016  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10247
+instret:1017  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10256
+instret:1018  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10265
+instret:1019  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10274
+instret:1020  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10283
+instret:1021  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10292
+instret:1022  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10301
+instret:1023  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10310
+instret:1024  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10319
+instret:1025  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10328
+instret:1026  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10337
+instret:1027  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10346
+instret:1028  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10355
+instret:1029  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10364
+instret:1030  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10373
+instret:1031  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10382
+instret:1032  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10391
+instret:1033  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10400
+instret:1034  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10409
+instret:1035  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10418
+instret:1036  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10427
+instret:1037  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10436
+instret:1038  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10445
+instret:1039  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10454
+instret:1040  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10463
+instret:1041  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10472
+instret:1042  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10481
+instret:1043  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10490
+instret:1044  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10499
+instret:1045  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10508
+instret:1046  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10517
+instret:1047  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10526
+instret:1048  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10535
+instret:1049  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10544
+instret:1050  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10553
+instret:1051  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10562
+instret:1052  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10571
+instret:1053  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10580
+instret:1054  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10589
+instret:1055  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10598
+instret:1056  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10607
+instret:1057  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10616
+instret:1058  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10625
+instret:1059  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10634
+instret:1060  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10643
+instret:1061  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10652
+instret:1062  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10661
+instret:1063  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10670
+instret:1064  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10679
+instret:1065  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10688
+instret:1066  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10697
+instret:1067  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10706
+instret:1068  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10715
+instret:1069  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10724
+instret:1070  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10733
+instret:1071  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10742
+instret:1072  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10751
+instret:1073  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10760
+instret:1074  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10769
+instret:1075  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10778
+instret:1076  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10787
+instret:1077  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10796
+instret:1078  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10805
+instret:1079  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10814
+instret:1080  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10823
+instret:1081  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10832
+instret:1082  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10841
+instret:1083  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10850
+instret:1084  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10859
+instret:1085  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10868
+instret:1086  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10877
+instret:1087  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10886
+instret:1088  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10895
+instret:1089  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10904
+instret:1090  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10913
+instret:1091  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10922
+instret:1092  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10931
+instret:1093  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10940
+instret:1094  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10949
+instret:1095  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10958
+instret:1096  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10967
+instret:1097  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10976
+instret:1098  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10985
+instret:1099  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      10994
+instret:1100  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11003
+instret:1101  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11012
+instret:1102  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11021
+instret:1103  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11030
+instret:1104  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11039
+instret:1105  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11048
+instret:1106  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11057
+instret:1107  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11066
+instret:1108  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11075
+instret:1109  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11084
+instret:1110  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11093
+instret:1111  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11102
+instret:1112  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11111
+instret:1113  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11120
+instret:1114  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11129
+instret:1115  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11138
+instret:1116  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11147
+instret:1117  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11156
+instret:1118  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11165
+instret:1119  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11174
+instret:1120  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11183
+instret:1121  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11192
+instret:1122  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11201
+instret:1123  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11210
+instret:1124  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11219
+instret:1125  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11228
+instret:1126  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11237
+instret:1127  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11246
+instret:1128  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11255
+instret:1129  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11264
+instret:1130  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11273
+instret:1131  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11282
+instret:1132  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11291
+instret:1133  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11300
+instret:1134  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11309
+instret:1135  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11318
+instret:1136  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11327
+instret:1137  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11336
+instret:1138  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11345
+instret:1139  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11354
+instret:1140  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11363
+instret:1141  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11372
+instret:1142  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11381
+instret:1143  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11390
+instret:1144  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11399
+instret:1145  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11408
+instret:1146  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11417
+instret:1147  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11426
+instret:1148  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11435
+instret:1149  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11444
+instret:1150  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11453
+instret:1151  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11462
+instret:1152  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11471
+instret:1153  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11480
+instret:1154  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11489
+instret:1155  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11498
+instret:1156  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11507
+instret:1157  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11516
+instret:1158  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11525
+instret:1159  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11534
+instret:1160  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11543
+instret:1161  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11552
+instret:1162  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11561
+instret:1163  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11570
+instret:1164  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11579
+instret:1165  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11588
+instret:1166  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11597
+instret:1167  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11606
+instret:1168  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11615
+instret:1169  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11624
+instret:1170  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11633
+instret:1171  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11642
+instret:1172  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11651
+instret:1173  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11660
+instret:1174  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11669
+instret:1175  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11678
+instret:1176  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11687
+instret:1177  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11696
+instret:1178  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11705
+instret:1179  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11714
+instret:1180  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11723
+instret:1181  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11732
+instret:1182  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11741
+instret:1183  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11750
+instret:1184  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11759
+instret:1185  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11768
+instret:1186  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11777
+instret:1187  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11786
+instret:1188  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11795
+instret:1189  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11804
+instret:1190  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11813
+instret:1191  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11822
+instret:1192  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11831
+instret:1193  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11840
+instret:1194  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11849
+instret:1195  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11858
+instret:1196  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11867
+instret:1197  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11876
+instret:1198  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11885
+instret:1199  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11894
+instret:1200  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11903
+instret:1201  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11912
+instret:1202  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11921
+instret:1203  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11930
+instret:1204  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11939
+instret:1205  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11948
+instret:1206  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11957
+instret:1207  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11966
+instret:1208  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11975
+instret:1209  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11984
+instret:1210  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      11993
+instret:1211  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12002
+instret:1212  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12011
+instret:1213  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12020
+instret:1214  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12029
+instret:1215  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12038
+instret:1216  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12047
+instret:1217  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12056
+instret:1218  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12065
+instret:1219  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12074
+instret:1220  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12083
+instret:1221  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12092
+instret:1222  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12101
+instret:1223  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12110
+instret:1224  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12119
+instret:1225  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12128
+instret:1226  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12137
+instret:1227  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12146
+instret:1228  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12155
+instret:1229  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12164
+instret:1230  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12173
+instret:1231  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12182
+instret:1232  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12191
+instret:1233  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12200
+instret:1234  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12209
+instret:1235  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12218
+instret:1236  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12227
+instret:1237  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12236
+instret:1238  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12245
+instret:1239  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12254
+instret:1240  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12263
+instret:1241  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12272
+instret:1242  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12281
+instret:1243  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12290
+instret:1244  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12299
+instret:1245  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12308
+instret:1246  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12317
+instret:1247  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12326
+instret:1248  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12335
+instret:1249  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12344
+instret:1250  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12353
+instret:1251  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12362
+instret:1252  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12371
+instret:1253  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12380
+instret:1254  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12389
+instret:1255  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12398
+instret:1256  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12407
+instret:1257  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12416
+instret:1258  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12425
+instret:1259  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12434
+instret:1260  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12443
+instret:1261  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12452
+instret:1262  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12461
+instret:1263  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12470
+instret:1264  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12479
+instret:1265  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12488
+instret:1266  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12497
+instret:1267  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12506
+instret:1268  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12515
+instret:1269  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12524
+instret:1270  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12533
+instret:1271  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12542
+instret:1272  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12551
+instret:1273  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12560
+instret:1274  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12569
+instret:1275  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12578
+instret:1276  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12587
+instret:1277  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12596
+instret:1278  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12605
+instret:1279  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12614
+instret:1280  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12623
+instret:1281  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12632
+instret:1282  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12641
+instret:1283  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12650
+instret:1284  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12659
+instret:1285  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12668
+instret:1286  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12677
+instret:1287  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12686
+instret:1288  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12695
+instret:1289  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12704
+instret:1290  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12713
+instret:1291  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12722
+instret:1292  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12731
+instret:1293  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12740
+instret:1294  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12749
+instret:1295  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12758
+instret:1296  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12767
+instret:1297  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12776
+instret:1298  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12785
+instret:1299  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12794
+instret:1300  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12803
+instret:1301  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12812
+instret:1302  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12821
+instret:1303  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12830
+instret:1304  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12839
+instret:1305  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12848
+instret:1306  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12857
+instret:1307  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12866
+instret:1308  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12875
+instret:1309  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12884
+instret:1310  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12893
+instret:1311  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12902
+instret:1312  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12911
+instret:1313  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12920
+instret:1314  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12929
+instret:1315  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12938
+instret:1316  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12947
+instret:1317  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12956
+instret:1318  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12965
+instret:1319  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12974
+instret:1320  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12983
+instret:1321  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      12992
+instret:1322  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13001
+instret:1323  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13010
+instret:1324  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13019
+instret:1325  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13028
+instret:1326  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13037
+instret:1327  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13046
+instret:1328  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13055
+instret:1329  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13064
+instret:1330  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13073
+instret:1331  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13082
+instret:1332  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13091
+instret:1333  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13100
+instret:1334  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13109
+instret:1335  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13118
+instret:1336  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13127
+instret:1337  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13136
+instret:1338  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13145
+instret:1339  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13154
+instret:1340  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13163
+instret:1341  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13172
+instret:1342  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13181
+instret:1343  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13190
+instret:1344  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13199
+instret:1345  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13208
+instret:1346  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13217
+instret:1347  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13226
+instret:1348  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13235
+instret:1349  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13244
+instret:1350  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13253
+instret:1351  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13262
+instret:1352  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13271
+instret:1353  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13280
+instret:1354  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13289
+instret:1355  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13298
+instret:1356  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13307
+instret:1357  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13316
+instret:1358  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13325
+instret:1359  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13334
+instret:1360  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13343
+instret:1361  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13352
+instret:1362  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13361
+instret:1363  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13370
+instret:1364  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13379
+instret:1365  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13388
+instret:1366  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13397
+instret:1367  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13406
+instret:1368  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13415
+instret:1369  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13424
+instret:1370  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13433
+instret:1371  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13442
+instret:1372  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13451
+instret:1373  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13460
+instret:1374  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13469
+instret:1375  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13478
+instret:1376  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13487
+instret:1377  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13496
+instret:1378  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13505
+instret:1379  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13514
+instret:1380  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13523
+instret:1381  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13532
+instret:1382  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13541
+instret:1383  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13550
+instret:1384  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13559
+instret:1385  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13568
+instret:1386  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13577
+instret:1387  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13586
+instret:1388  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13595
+instret:1389  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13604
+instret:1390  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13613
+instret:1391  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13622
+instret:1392  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13631
+instret:1393  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13640
+instret:1394  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13649
+instret:1395  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13658
+instret:1396  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13667
+instret:1397  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13676
+instret:1398  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13685
+instret:1399  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13694
+instret:1400  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13703
+instret:1401  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13712
+instret:1402  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13721
+instret:1403  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13730
+instret:1404  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13739
+instret:1405  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13748
+instret:1406  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13757
+instret:1407  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13766
+instret:1408  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13775
+instret:1409  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13784
+instret:1410  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13793
+instret:1411  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13802
+instret:1412  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13811
+instret:1413  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13820
+instret:1414  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13829
+instret:1415  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13838
+instret:1416  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13847
+instret:1417  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13856
+instret:1418  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13865
+instret:1419  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13874
+instret:1420  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13883
+instret:1421  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13892
+instret:1422  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13901
+instret:1423  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13910
+instret:1424  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13919
+instret:1425  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13928
+instret:1426  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13937
+instret:1427  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13946
+instret:1428  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13955
+instret:1429  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13964
+instret:1430  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13973
+instret:1431  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13982
+instret:1432  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      13991
+instret:1433  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14000
+instret:1434  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14009
+instret:1435  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14018
+instret:1436  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14027
+instret:1437  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14036
+instret:1438  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14045
+instret:1439  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14054
+instret:1440  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14063
+instret:1441  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14072
+instret:1442  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14081
+instret:1443  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14090
+instret:1444  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14099
+instret:1445  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14108
+instret:1446  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14117
+instret:1447  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14126
+instret:1448  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14135
+instret:1449  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14144
+instret:1450  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14153
+instret:1451  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14162
+instret:1452  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14171
+instret:1453  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14180
+instret:1454  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14189
+instret:1455  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14198
+instret:1456  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14207
+instret:1457  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14216
+instret:1458  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14225
+instret:1459  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14234
+instret:1460  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14243
+instret:1461  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14252
+instret:1462  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14261
+instret:1463  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14270
+instret:1464  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14279
+instret:1465  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14288
+instret:1466  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14297
+instret:1467  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14306
+instret:1468  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14315
+instret:1469  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14324
+instret:1470  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14333
+instret:1471  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14342
+instret:1472  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14351
+instret:1473  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14360
+instret:1474  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14369
+instret:1475  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14378
+instret:1476  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14387
+instret:1477  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14396
+instret:1478  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14405
+instret:1479  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14414
+instret:1480  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14423
+instret:1481  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14432
+instret:1482  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14441
+instret:1483  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14450
+instret:1484  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14459
+instret:1485  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14468
+instret:1486  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14477
+instret:1487  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14486
+instret:1488  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14495
+instret:1489  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14504
+instret:1490  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14513
+instret:1491  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14522
+instret:1492  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14531
+instret:1493  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14540
+instret:1494  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14549
+instret:1495  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14558
+instret:1496  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14567
+instret:1497  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14576
+instret:1498  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14585
+instret:1499  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14594
+instret:1500  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14603
+instret:1501  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14612
+instret:1502  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14621
+instret:1503  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14630
+instret:1504  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14639
+instret:1505  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14648
+instret:1506  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14657
+instret:1507  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14666
+instret:1508  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14675
+instret:1509  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14684
+instret:1510  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14693
+instret:1511  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14702
+instret:1512  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14711
+instret:1513  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14720
+instret:1514  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14729
+instret:1515  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14738
+instret:1516  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14747
+instret:1517  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14756
+instret:1518  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14765
+instret:1519  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14774
+instret:1520  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14783
+instret:1521  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14792
+instret:1522  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14801
+instret:1523  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14810
+instret:1524  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14819
+instret:1525  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14828
+instret:1526  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14837
+instret:1527  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14846
+instret:1528  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14855
+instret:1529  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14864
+instret:1530  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14873
+instret:1531  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14882
+instret:1532  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14891
+instret:1533  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14900
+instret:1534  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14909
+instret:1535  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14918
+instret:1536  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14927
+instret:1537  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14936
+instret:1538  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14945
+instret:1539  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14954
+instret:1540  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14963
+instret:1541  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14972
+instret:1542  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14981
+instret:1543  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14990
+instret:1544  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      14999
+instret:1545  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15008
+instret:1546  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15017
+instret:1547  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15026
+instret:1548  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15035
+instret:1549  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15044
+instret:1550  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15053
+instret:1551  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15062
+instret:1552  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15071
+instret:1553  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15080
+instret:1554  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15089
+instret:1555  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15098
+instret:1556  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15107
+instret:1557  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15116
+instret:1558  PC:0x1ffff0000000000000000000000000000  instr:0x00000000  iType:Unsupported    [doCommitTrap]      15125
diff --git a/src_Core/CPU/Core.bsv b/src_Core/CPU/Core.bsv
index de2968e..4d374b4 100644
--- a/src_Core/CPU/Core.bsv
+++ b/src_Core/CPU/Core.bsv
@@ -918,7 +918,7 @@ module mkCore#(CoreId coreId)(Core);
     // incr cycle count
     (* fire_when_enabled, no_implicit_conditions *)
     rule incCycleCnt(doStats);
-        $display("calling cycle");
+        // $display("calling cycle");
         cycleCnt.incr(1);
     endrule
 
@@ -963,7 +963,6 @@ module mkCore#(CoreId coreId)(Core);
     // broadcast whether we should collect data
     rule broadcastDoStats;
         let stats = csrf.doPerfStats;
-        $display("[stats] enabled %0d",  csrf.doPerfStats);
         doStats <= stats;
         iMem.perf.setStatus(stats);
         dMem.perf.setStatus(stats);
diff --git a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
index 8461f62..0833697 100644
--- a/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
+++ b/src_Core/RISCY_OOO/procs/RV64G_OOO/MemExePipeline.bsv
@@ -653,8 +653,15 @@ module mkMemExePipeline#(MemExeInput inIfc)(MemExePipeline);
 `endif
         // Test delta value read from the pointer
         Bit#(25) delta = decodeDelta(x.vaddr);
-        $display("Decoded delta = %0d", delta);
-        x.vaddr = encodeDelta(x.vaddr, 0);
+        $display("Decoded delta from register = %0d", delta);
+
+        // 33554431 is 2^25 - 1 (all ones)
+        if (delta == 33554431) begin
+            delta = 0;
+        end else begin
+            x.vaddr = encodeDelta(x.vaddr, 0);
+        end
+        // x.vaddr = encodeDelta(x.vaddr, 0);
         // x.vaddr = (x.vaddr >> 25) << 25;
         // x.vaddr = (x.vaddr >> 25) << 25;
 
diff --git a/src_Core/RISCY_OOO/procs/lib/Exec.bsv b/src_Core/RISCY_OOO/procs/lib/Exec.bsv
index 7a60871..a76b2e8 100644
--- a/src_Core/RISCY_OOO/procs/lib/Exec.bsv
+++ b/src_Core/RISCY_OOO/procs/lib/Exec.bsv
@@ -244,7 +244,7 @@ function CapPipe capModify(CapPipe a, CapPipe b, CapModifyFunc func);
     // TODO: Delta handler function 
     CapPipe res = (case(func) matches
             tagged ModifyOffset .offsetOp :
-                //modifyOffset(a_mut, getAddr(b), offsetOp == IncOffset).value;
+                // modifyOffset(a_mut, getAddr(b), offsetOp == IncOffset).value;
                 // To test this
                 encodeDelta(a_mut, getAddr(b));
             tagged SetBounds .boundsOp    :